71V2556S150PFGI IDT, 71V2556S150PFGI Datasheet - Page 8

• Manufacturer Part Number: 71V2556S150PFGI
• Description: SRAM
• Manufacturer: IDT

Specifications of 71V2556S150PFGI

• Rohs: yes
• Part # Aliases: IDT71V2556S150PFGI

Interleaved Burst Sequence Table
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram
NOTES:
1. This assumes CEN, CE
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
F
e S
F
F
e S
F
h T
h T
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
s r i
u o
s r i
u o
(R/W, ADV/LD, BWx)
d r i
d r i
o c
o c
delay from the rising edge of clock.
I/O [0:31], I/O P[1:4]
A t
A t
h t r
h t r
d n
d n
A
A
d d
d d
CONTROL
ADDRESS
A
A
d d
d d
d d
d d
(A0 - A16)
A
A
e r
e r
CLOCK
DATA
e r
e r
CYCLE
d d
d d
s s
e r
s s
e r
s s
s s
e r
e r
s s
s s
s s
s s
) 1 (
) 1 (
(2)
(2)
(2)
1
, CE
2
, CE
D/Q27
n+29
C29
A29
2
are all true.
D/Q28
n+30
C30
A30
1 A
1 A
0
0
0
0
1
1
1
1
e S
e S
u q
u q
(1)
D/Q29
n e
n e
n+31
C31
A31
e c
(LBO=V
e c
1
1
0 A
0 A
0
0
1
1
0
0
1
1
D/Q30
(LBO=V
n+32
C32
A32
6.42
SS
8
)
1 A
1 A
0
0
1
1
0
0
1
1
e S
e S
u q
u q
DD
D/Q31
n e
n e
n+33
C33
A33
e c
e c
)
2
2
0 A
0 A
0
0
1
1
0
0
1
1
Commercial and Industrial Temperature Ranges
D/Q32
n+34
C34
A34
1 A
1 A
0
0
1
1
0
0
1
1
e S
e S
u q
u q
D/Q33
n e
n e
n+35
C35
A35
e c
e c
3
3
0 A
0 A
0
0
1
1
0
0
1
1
D/Q34
n+36
C36
A36
1 A
1 A
0
0
1
1
0
0
1
1
e S
e S
u q
u q
4875 drw 03
D/Q35
n e
n e
n+37
C37
A37
e c
e c
4
4
8 4
0 A
0 A
8 4
0
0
1
1
0
0
5 7
1
1
5 7
l b t
l b t
0 1
1 1
,