NAND16GW3F2AN6E NUMONYX, NAND16GW3F2AN6E Datasheet
NAND16GW3F2AN6E
Specifications of NAND16GW3F2AN6E
Related parts for NAND16GW3F2AN6E
NAND16GW3F2AN6E Summary of contents
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... Serial number (unique ID) Development tools – Error correction code models – Bad block management and wear leveling algorithm – HW simulation models Data integrity – 100,000 program/erase cycles (with ECC) – 10 years data retention RoHS compliant packages Rev 5 Preliminary Data 1/65 www.numonyx.com 1 ...
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... Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Inputs/outputs (I/O0-I/O7 3.2 Address Latch Enable (AL 3.3 Command Latch Enable (CL 3.4 Chip Enable ( 3.5 Read Enable ( 3.6 Write Enable ( 3.7 Write Protect (WP 3.8 Ready/Busy (RB 3.9 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 Write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5.1 9.5.2 10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 49 11 Maximum ratings ...
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Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND08GW3F2A, NAND16GW3F2A List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10 ...
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... It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. The device is available in TSOP48 (12 × 20 mm) package. and is shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’. ...
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... V 64 pages bytes x 8192 blocks P/E/R controller high voltage generator RB NAND08GW3F2A, NAND16GW3F2A Timings Sequential Page Block access program erase time (min) (typ) (typ) 1 500 µs TSOP48 ms NAND flash memory array Page buffer Y decoder Buffers I/O AI13296c Package ...
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NAND08GW3F2A, NAND16GW3F2A Figure 2. Logic diagram Table 2. Signal names Signal I/ NAND flash Function ...
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Description Figure 3. TSOP48 connections 10/65 NAND08GW3F2A, NAND16GW3F2A NAND flash ...
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... Memory array organization The memory array is comprised of NAND structures where 32 cells are connected in series organized into blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array stores data, whereas the spare area typically stores software flags or bad block identification ...
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... Memory array organization Figure 4. Memory array organization Main area Block page 4096 bytes Page buffer, 4224 bytes 4096 bytes 12/65 x8 bus width Plane = 2048 blocks Block = 64 pages Page = 4224 bytes (4096+128) First plane Second plane Main area 4096 bytes 128 128 ...
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... When CL is High, the inputs are latched on the rising edge of Write Enable. 3.4 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V High while the device is busy, the device remains selected and does not go into IH standby mode ...
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... V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 19: DC characteristics) to protect the device from any involuntary program/erase during power transitions ...
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... NAND08GW3F2A, NAND16GW3F2A 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section. See the summary in Typically, glitches of less than Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. ...
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... The Write Protect signal is not latched by Write Enable to ensure protection, even during power-up. 4.6 Standby The memory enters standby mode by holding Chip Enable, E, High for at least 10 µs. In standby mode, the device is deselected, outputs are disabled and power consumption is reduced. Table 4. ...
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NAND08GW3F2A, NAND16GW3F2A Table 6. Address definitions Address A0 - A12 A13 - A18 A19 - A31 Bus operations Definition Column address Page address Block address 17/65 ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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NAND08GW3F2A, NAND16GW3F2A 6 Device operations 6.1 Single plane operations This section gives the details of the single plane device operations. 6.1.1 Page read At power-up the device defaults to read mode. To enter read mode from another mode the Read ...
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Device operations Figure 5. Random data output tBLBH1 (Read Busy time Address I/O 00h 30h inputs Cmd Cmd code code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main area 6.1.2 Cache read The cache read operation ...
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... Setup code 6.1.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, data is programmed sequentially, however, the device does support random input within a page. The memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 4224) can be programmed. ...
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Device operations Figure 7. Page program operation RB I/O 80h Page program setup code Once the program operation has started the status register can be read using the Read Status Register command. During program operations the status register only flags ...
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NAND08GW3F2A, NAND16GW3F2A Figure 8. Random data input during sequential data input RB Address I/O 80h Data input inputs Cmd code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main area 6.1.4 Block erase Erase operations are done one block ...
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... During the copy back program, data modification is possible using Random Data Input command (85h) as shown in program operation with random data The copy back program operation is only allowed within the same memory plane (A19 and A31 fixed for source and target address). 24/65 ...
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NAND08GW3F2A, NAND16GW3F2A Figure 10. Copy back program operation (without readout of data) Source I/O 00h Add inputs Read code (Read Busy time) RB Figure 11. Copy back program operation (with readout of data) Source I/O 35h 00h Add Inputs Read ...
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... Multiplane page read The multiplane page read operation is an extension of a page read operation for a single plane. Since the device is equipped with two memory planes, a read of two pages (one for each plane) is enabled by activating two sets of 4224-byte page registers (one for each plane) ...
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NAND08GW3F2A, NAND16GW3F2A Figure 13. Multiplane page read operation with sequential and random data output Add. 3 I/O 60h 60h cycles Row Add A13-A18 = fixed 'Low' A19 = fixed 'Low' A20-A30 = ...
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Device operations 6.2.2 Multiplane cache read NANDxxGW3F2A devices have a multiplane page read with cache operation, which enables much higher speed read operation compared to page read operation. The restrictions for this operation are shown in cache read. Figure 14. ...
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... The second step programs, in parallel, the two pages of data loaded into the data buffer into the appropriate memory pages started by issuing a Program Confirm command. As for standard page program operations, the device supports random data input during both data loading phases. ...
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Device operations Figure 15. Multiplane page program operation RB I/O Data input 80h Address inputs Page program A0-A12 = Valid setup code A13-A18 = fixed 'Low' A19 = fixed 'Low' A20-A30 = fixed 'Low' A31 = fixed 80h Data input ...
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... Since the device is equipped with two memory planes, activating the two sets of 4224-byte page registers enables a simultaneous programming of two pages. ...
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Device operations Figure 17. Multiplane copy back program operation RB Address I/O 60h 60h (3 cycles) Row add: 1,2,3 Row add: 1,2,3 A13-A18 = fixed 'Low' A13-A18 = Valid A19 = fixed 'Low' A20-A30 = fixed 'Low' A20-A30 = Valid ...
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NAND08GW3F2A, NAND16GW3F2A Figure 18. Multiplane copy back program operation with random data input RB Address I/O 60h 60h (3 cycles) Row add: 1,2,3 Row add: 1,2,3 A13-A18 = fixed 'Low' A13-A18 = Valid A19 = fixed 'Low' A20-A30 = fixed ...
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Device operations Figure 19. Multiplane copy back operation sequence RB Row addr. I/O 60h 60h (3 cycles) Address I/O 00h 05h (5 cycles) RB Address Data in I/O 85h (5 cycles) x bytes Address I/O 00h (5 cycles) RB Address ...
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NAND08GW3F2A, NAND16GW3F2A Figure 21. New multiplane copy back operation sequence RB Row addr. I/O 60h 60h (3 cycles) Address I/O 00h 05h (5 cycles) Address I/O 85h (5 cycles) Address I/O 00h 05h (5 cycles) RB Address Data in I/O ...
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Device operations Figure 22. New multiplane copy back operation flow 36/65 NAND08GW3F2A, NAND16GW3F2A ...
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NAND08GW3F2A, NAND16GW3F2A 6.3 2-Kbyte page backward compatibility 6.3.1 Page program with 2-Kbyte page compatibility A special page program operation is provided for 2-Kbyte compatibility, as shown in Figure 23: Page program with 2-Kbyte page Figure 23. Page program with 2-Kbyte ...
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... A31 = fixed RB 1. Copy back program operation is allowed only within the same memory plane the same plane not allowed to operate a copy-back program from an odd address page (source page even address page (target page) or from an even address page (source page odd address page (target page). Therefore, the copy-back program is permitted only between odd address pages or even address pages ...
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... The Reset command reset the command interface and status register. If the Reset command is issued during any operation, the operation is aborted program or erase operation that is being aborted, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. ...
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... The error bit identifies if any errors have been detected by the P/E/R controller. The error bit is set to ‘1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’, the operation has completed successfully. 6.6 Read electronic signature The device contains a manufacturer code and device code ...
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NAND08GW3F2A, NAND16GW3F2A Table 11. Electronic signature byte 3 I/O I/O1-I/O0 I/O3-I/O2 Number of simultaneously I/O5-I/O4 programmed pages Interleaved programming I/O6 between multiple devices I/O7 Table 12. Electronic signature byte 4 I/O I/O1-I/O0 (without spare area) Spare area size I/O2 (byte/512 ...
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Data protection Table 13. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 - I/O2 I/O6 - I/O4 I/O7 7 Data protection The device has hardware features to protect against spurious program and erase operations. An internal voltage detector disables ...
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NAND08GW3F2A, NAND16GW3F2A 8 Write protect operation Erase and program operations are automatically reset when WP goes Low (t Erase and program operations are enabled and disabled as shown in Figure 29, and Figure If WP goes Low after the device ...
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... To help integrate a NAND memory into an application, Numonyx can provide a full range of software solutions: file system, sector manager, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...
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... Program command can be used to copy the data to a valid block. See Random data input during sequential data input Read failure in this case, ECC correction must be implemented. To efficiently use the memory space recommended to recover single-bit errors in read by ECC, without replacing the whole block. ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations recommended to implement a garbage collection algorithm garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 32) ...
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NAND08GW3F2A, NAND16GW3F2A 9.4 Wear-leveling algorithm For write-intensive applications recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. In memories that do not use a wear-leveling algorithm, not all blocks get ...
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Software algorithms 9.5 Hardware simulation models 9.5.1 Behavioral simulation models Denali software corporation models are platform-independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND flash ...
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NAND08GW3F2A, NAND16GW3F2A 10 Program and erase times and endurance cycles Table 15 shows the program and erase times and the number of program/erase cycles per block. Table 15. Program and erase times and program erase endurance cycles Page program time ...
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Maximum ratings 11 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the ...
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NAND08GW3F2A, NAND16GW3F2A 12 DC and AC parameters This section summarizes the operating and measurement conditions as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristics tables are derived from tests ...
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DC and AC parameters Table 19. DC characteristics Symbol Parameter I DD1 Operating I current DD2 I DD3 Standby current (TTL) I DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input ...
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NAND08GW3F2A, NAND16GW3F2A Table 21. AC characteristics for operations Alt. Symbol symbol t ALLRL1 t Address Latch Low to Read Enable Low AR t ALLRL2 t t BHRL BLBH1 RBSY t t Ready/Busy Low to Ready/Busy High BLBH2 ...
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DC and AC parameters Figure 33. Command latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 34. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W ...
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NAND08GW3F2A, NAND16GW3F2A Figure 35. Data input latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 36. Sequential data output after read AC waveforms E tRLRH R tELQV tRLQV (R Accesstime) I/O tBHRL RB ...
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DC and AC parameters Figure 37. Read status register AC waveforms CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 38. Read electronic signature AC waveforms I/O 90h Read Electronic Signature command 1. ...
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NAND08GW3F2A, NAND16GW3F2A Figure 39. Page read operation AC waveforms CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N input code tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N ...
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DC and AC parameters Figure 40. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program setup code 58/65 tWLWL tWHWH Add.N Add.N Add.N N cycle ...
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NAND08GW3F2A, NAND16GW3F2A Figure 41. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input setup command Figure 42. Reset AC waveforms I/O ...
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DC and AC parameters 12.1 Ready/Busy signal electrical characteristics Figure 44, Figure 43 signal. The value required for the resistor R So, where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. ...
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NAND08GW3F2A, NAND16GW3F2A Figure 45. Resistor value versus waveform timings for Ready/Busy signal °C. DC and AC parameters 61/65 ...
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... Package mechanical 13 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. Ordering information NAND08G ...
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Revision history 15 Revision history Table 24. Document revision history Date 06-Aug-2008 30-Oct-2008 24-Sep-2009 07-Oct-2009 19-Nov-2009 64/65 Revision 1 Initial release. Document status promoted from target specification to preliminary 2 data. Added information about the OTP area security feature. Added ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...