NAND16GW3F2AN6E NUMONYX, NAND16GW3F2AN6E Datasheet - Page 22

• Manufacturer Part Number: NAND16GW3F2AN6E
• Description: IC FLASH 16GBIT SLC 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND16GW3F2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 16G (2G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Device operations
Figure 7.
22/65
RB
I/O
Page program operation
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to ‘1’ that have not been successfully programmed to ‘0’.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored. Once the program operation has completed, the
P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input, each page program operation comprises five steps:
1.
2.
3.
4.
5.
Random data input
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address issuing a Random Data Input command. The following two
steps are required to issue the command:
1.
2.
Random data input operations can be repeated as often as required in any given page.
Page program
setup code
One bus cycle is required to set up the Page Program (sequential input) command (see
Table 7: Command
Five bus cycles are then required to input the program address (refer to
Address
The data is loaded into the data registers
One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R controller only starts if the data has been loaded in step 3
The P/E/R controller then programs the data into the array.
One bus cycle is required to setup the Random Data Input command (see
Two bus cycles are then required to input the new column address (refer to
80h
insertion)
Address inputs
set)
Data input
(Program Busy time)
Confirm
NAND08GW3F2A, NAND16GW3F2A
code
10h
tBLBH2
Busy
Read status register
70h
Table 5:
Table
SR0
Table
ai08659
7).
5).