DS28E04S-100+ Maxim Integrated Products, DS28E04S-100+ Datasheet
DS28E04S-100+
Specifications of DS28E04S-100+
Related parts for DS28E04S-100+
DS28E04S-100+ Summary of contents
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... EEPROM · · § § § § § § § ORDERING INFORMATION DS28E04S-100 DS28E04S-100/T&R -40°C to +85°C Tape-and-Reel PIN CONFIGURATION POL P1 P0 GND A0 RST1 RST0 DS28E04 #7 Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp. ...
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ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND All Pins: Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ...
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PARAMETER SYMBOL IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time (Note 1) t RSTL Presence-Detect High t PDH Time Presence-Detect Fall Time t FPD (Notes 3, 18) Presence-Detect Low t PDL Time Presence-Detect Sample t MSP Time (Note ...
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... PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory location ...
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... OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The hierarchical structure of the 1-Wire protocol is shown in Figure 2 ...
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... Device ID, RC-Flag, PIO Status, cond. Search Settings RC-Flag RC-Flag RC-Flag, OD-Flag Device ID, RC-Flag, OD-Flag 32-byte Scratchpad, Flags 32-byte Scratchpad Data Memory, Register Page Data Memory, Registers PIO Pins PIO Pins, Activity Latch PIO Pins, Activity Latch Activity Latch Conditional Search and Control Registers ...
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... The protection control registers, along with the register page lock byte, determine whether write protection, EPROM mode, or copy protection is enabled for each of the 16 data memory pages. A value of 55h sets write protection for the associated memory page. A value of AAh sets EPROM mode. A value of 55h or AAh for the register page lock byte sets copy protection for all write-protected data memory pages, as well as the register page ...
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... Write Protected; AAh: EPROM mode. Address 0200h is associated with memory page 0, address 0201h with page 1, etc. (See text) (Reads 55h or AAh) (Undefined value) (The lower two bits are valid) ...
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... The logic state of the PIO pins can be obtained by reading this register using the Read Memory command. This register is read-only. Each bit is associated with the pin of the respective PIO channel. Bits have no function; they always read 1. The data in this register reflects the PIO state at the last (most significant) bit of the byte that proceeds reading the first (least significant) bit of this register ...
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... The data in this register represents the current state of the PIO activity latches. This register is read using the Read Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO channel. Bits have no function; they always read 0. A state transition on a PIO pin, HighèLow or Lowè ...
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Conditional Search Channel Polarity Selection Register ADDR b7 b6 0224h 0 0 The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. This register can only be ...
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ADDRESS REGISTERS AND TRANSFER STATUS The DS28E04-100 employs three address registers, called TA1, TA2, and E/S (Figure 8). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data ...
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... After waiting 10ms, the master may issue read time slots to receive AAh confirmation bytes until the master issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA flag will not be set. ...
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... Figure 9-1. Memory/Control Function Flow Chart TA1 (T7:T0), TA2 (T15:T8) DS28E04 Increments Scratchpad Offset Bus Master RX “1”s Bus Master TX Memory Function Command 0Fh N Write Scratch- pad ? Y Bus Master TX EEPROM Array Target Address DS28E04 sets Scratchpad Offset = (T4:T0), Clears PF, AA Master TX Data Byte ...
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... Figure 9-2. Memory/Control Function Flow Chart (continued) From Figure Part DS28E04 Increments Scratchpad Offset Bus Master RX “1”s To Figure Part AAh N Read Scratch- Pad ? Y Bus Master RX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte DS28E04 sets Scratchpad Offset = (T4:T0) Bus Master RX Data Byte ...
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... Figure 9-3. Memory/Control Function Flow Chart (continued) From Figure Part Copy Scratch- Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Auth. Code Bus Master TX Reset ? To Figure Part 55h N Pad ? Y Applicable to all R/W memory locations. Y T15:T0 Match ? < 0220h ? “1”s N Master ...
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... Figure 9-4. Memory/Control Function Flow Chart (continued) From Figure 9 rd F0h 3 Part Read Memory ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Y Address < 226h ? N DS28E04 Increments Address Counter Y Bus Master RX “1”s To Figure Part N Y DS28E04 sets Memory Address = (T15:T0) Bus Master RX Data Byte from ...
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... Figure 9-5. Memory/Control Function Flow Chart (continued) From Figure Part Note 1) DS28E04 Samples See the command description for the exact timing of the PIO pin sampling and updating. Y Bus Master RX PIO Pin Status Bus Master RX CRC16 of Command and 32 Bytes of PIO st Pin Status (1 ...
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... Figure 9-6. Memory/Control Function Flow Chart (continued) From Figure Part PIO Access Pulse? Note 1) Bus Master TX PIO See the command Selection Mask description for the exact timing of the Bus Master TX PIO pin sampling inverted PIO and updating. Selection Mask Transmission DS28E04 Initiates ...
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... Next the master sends the byte to be written to the addressed cell. If the address was valid, the byte is immediately written to its memory location. The master now can either end the command by issuing a 1-Wire reset or send another byte for the next higher address. Once memory address 0225h has been written, any subsequent data bytes will be ignored ...
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PIO ACCESS WRITE [5Ah] The PIO Access Write command is the only way to write to the PIO output-latch state register (address 0221h), which controls the open-drain output transistors of the PIO channels endless loop, this command first ...
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Figure 12. PIO Access Pulse Timing Diagram IO PIO RESET ACTIVITY LATCHES [C3h] Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin of duration greater than t . This ...
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... DS28E04-100 on a multidrop bus. Only the DS28E04-100 that exactly matches the 64-bit ROM sequence, including the external address, responds to the following Memory/Control Function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. ...
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... To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and set, directly transfers control to the Memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command ...
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... Master TX Bit 1 Master TX Bit Bit 1 Bit 1 Match? Match? Y DS28E04 Master TX Bit 63 DS28E04 Master TX Bit Bit 63 Bit 63 Match? Match Memory Functions Flow Chart (Figure From Figure 14 Figure 14 ECh N Cond. Search Command CSR = 1? Y DS28E04 TX Bit 0 DS28E04 TX Bit 0 Master TX Bit 0 N Bit 0 Match? ...
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Figure 14-2. ROM Functions Flow Chart (continued Figure 14, 1 Part From Figure Part CCh N Skip ROM Command From Figure Part To Figure Part ...
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... Figure 15 shows the initialization sequence required to begin any communication with the DS28E04-100. A Reset Pulse followed by a Presence Pulse indicates the DS28E04-100 is ready to receive data, given the correct ROM and Memory/Control Function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for compensate for the edge ...
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Read/Write Time Slots Data communication with the DS28E04-100 takes place in time slots, which carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 16 ...
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Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V low time t is expired. For a write-zero time slot, the voltage on the data line must stay below the V W1LMAX threshold ...
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Figure 17. Noise Suppression Scheme V PUP Case A 0V CRC GENERATION With the DS28E04-100 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte ...
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... Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. <data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. <register data> Data for registers at addresses 223h to 225h bytes, depending on start address. CRC16\ Transfer of an inverted CRC16 ...
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... COPY SCRATCHPAD 1-Wire POWERED (SUCCESS) RST PD Select CPS COPY SCRATCHPAD (INVALID ADDRESS COPY PROTECTED) RST PD Select CPS READ MEMORY (SUCCESS) RST PD Select RM READ MEMORY (INVALID ADDRESS) RST PD Select RM WRITE REGISTER (SUCCESS) RST PD Select WREG WRITE REGISTER (INVALID ADDRESS) RST PD Select WREG ...
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PIO ACCESS READ (CANNOT FAIL) RST PD Select PIOR PIO ACCESS WRITE (SUCCESS) RST PD Select PIOW INVALID DATA BYTE PIO ACCESS WRITE ( RST PD Select PIOW PIO ACCESS PULSE (SUCCESS) RST PD Select PIOP INVALID SELECTION MASK PIO ...
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... MEMORY FUNCTION EXAMPLE Write 5 bytes to memory page 1, starting at address 0021h. Read the entire memory and the PIO-related registers. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE ---- DATA (LSB FIRST) (Reset) Reset pulse (Presence) Presence pulse CCh Issue “ ...
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PIO ACCESS READ EXAMPLE Read the state of the PIOs 32 times. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE The inverted CRC16 ...
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PIO ACCESS PULSE EXAMPLE Generate a pulse on PIO1. Both PIOs are pulled high to V With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE ...