DS28E04S-100+ Maxim Integrated Products, DS28E04S-100+ Datasheet - Page 22

• Manufacturer Part Number: DS28E04S-100+
• Description: IC EEPROM 4KBIT 16SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS28E04S-100+

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (256 x 16)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Organization: 4 K x 1
• Interface Type: 1-Wire
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 12. PIO Access Pulse Timing Diagram
RESET ACTIVITY LATCHES [C3h]
Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin of duration
greater than t
generating a pulse. Depending on the application there may be a need to reset the activity latch after having
captured and serviced an external event. Since there is only read access to the PIO Activity Latch State Register,
the DS28E04-100 supports a special command to reset these latches. After having received the command code,
the device resets all activity latches simultaneously. There are two ways for the master to verify the execution of
the Reset Activity Latches command. One way is to start reading from the 1-Wire line right after the command code
is transmitted. In this case, the master reads AAh bytes until it sends a 1-Wire reset. The other way is reading
register address 0222h.
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E04-
100 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken
down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and
timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are
initiated on the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state
outputs. The 1-Wire port of the DS28E04-100 is open drain with an internal circuit equivalent to that shown in
Figure 13.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E04-100 supports both a
standard and Overdrive communication speed of 15.4kbps (max) and 111kbps (max), respectively. Note that
legacy 1-Wire products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The
slightly reduced rates for the DS28E04-100 are a result of additional recovery times, which in turn were driven by a
1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primarily
depends on the network size and load conditions. The DS28E04-100 requires a pullup resistor of 2.2kW (max) at
any speed.
The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs
(Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus can be reset.
PWMIN
. This change can be caused by an external event/signal or by writing to the PIO or by
PIO
IO
MS 2 bits of inverted
Selection Mask
POL=1
POL=0
t
REH
V
+x
22 of 36
TH
LS 2 bits of confir-
mation byte (AAh)
t
PULSE