MAX691ACSE-T Maxim Integrated, MAX691ACSE-T Datasheet - Page 9

• Manufacturer Part Number: MAX691ACSE-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX691A, MAX693A, MAX800, MAX800L, MAX800Mr

Specifications of MAX691ACSE-T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 0 V to 5.5 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16 Narrow
• Chip Enable Signals: Yes
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: 0 C
• Power Fail Detection: Yes
• Supply Current (typ): 100 uA
• Supply Voltage - Min: 0 V

Table 1. Reset Pulse Width and Watchdog Timeout Selections
Figure 3. Oscillator Circuits
The MAX691A/MAX693A/MAX800L/MAX800M provide
internal gating of chip-enable (CE) signals to prevent
erroneous data from being written to CMOS RAM in the
event of a power failure. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled, prevent-
ing erroneous data from corrupting the CMOS RAM. All
these parts use a series transmission gate from
CE OUT (Figure 4).
The 10ns max CE propagation delay from CE IN to CE
OUT enables the parts to be used with most µPs.
The Chip-Enable Input (CE IN) is high impedance (dis-
abled mode) while RESET and RESET are asserted.
During a power-down sequence where V
the reset threshold or a watchdog fault,
a high-impedance state when the voltage at CE IN
goes high or 15µs after reset is asserted, whichever
occurs first (Figure 5).
During a power-up sequence, CE IN remains high
impedance, regardless of CE IN activity, until reset is
deasserted following the reset timeout period.
MAX800M
MAX691A
MAX693A
MAX800L
OSC SEL
Floating
Floating
Low
Low
50kHz
N.C.
N.C.
INTERNAL OSCILLATOR
_______________________________________________________________________________________
8
8
7
7
1.6s WATCHDOG
External Clock Input
OSC SEL
OSC IN
OSC SEL
OSC IN
External Capacitor
Chip-Enable Signal Gating
EXTERNAL
CLOCK
Floating
OSC IN
Microprocessor Supervisory Circuits
Low
N.C.
Chip-Enable Input
INTERNAL OSCILLATOR
8
100ms WATCHDOG
8
7
7
–
CE IN assumes
CC
OSCILLATOR
OSC SEL
OSC IN
OSC SEL
OSC IN
EXTERNAL
falls below
(600/47pF x C)ms
–
CE IN to
1024 clks
Normal
100ms
1.6s
Watchdog Timeout Period
In the high-impedance mode, the leakage currents into
this terminal are ±1µA max over temperature. In the
low-impedance mode, the impedance of
as a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to
Enable Output (
Delay vs. CE OUT Load Capacitance in the Typical
Operating Characteristics ). The CE propagation delay
is production tested from the 50% point of
50% point of
load capacitance (Figure 6). For minimum propagation
delay, minimize the capacitive load at CE OUT, and
use a low output-impedance driver.
In the enabled mode, the impedance of CE OUT is
equivalent to 75Ω in series with the source driving CE
IN. In the disabled mode, the 75Ω transmission gate is
off and CE OUT is actively pulled to V
turns off when the transmission gate is enabled.
LOW LINE is the buffered output of the reset threshold
comparator. LOW LINE typically sinks 3.2mA at 0.1V.
For normal operation (V
old), LOW LINE is pulled to V
The power-fail comparator is an uncommitted comparator
that has no effect on the other functions of the IC.
Common uses include low-battery indication (Figure 7),
and early power-fail warning (see Typical Operating
Circuit ).
Power-Fail Input (PFI) is the input to the power-fail com-
parator. It has a guaranteed input leakage of ±25nA
max over temperature. The typical comparator delay is
25µs from V
to V
nect it to ground.
OH
Immediately After Reset
(power being restored). If PFI is not used, con-
–
CE IN and the capacitive loading on the Chip-
(2.4/47pF x C)sec
IL
4096 clks
–
CE OUT using a 50Ω driver and 50pF of
to V
1.6s
1.6s
–
CE OUT) (see Chip-Enable Propagation
OL
(power failing), and 60µs from V
CC
Power-Fail Comparator
above the LOW LINE thresh-
OUT
.
Reset Timeout Period
–
L
—
(1200/47pF x C)ms
Chip-Enable Output
O
—
W
— —
OUT
Power-Fail Input
2048 clks
L
200ms
200ms
—
–
CE IN appears
—
I
. This source
N
—
–
CE IN to the
E
–
Output
IH
9