CY7C1412AV18-167BZC Cypress Semiconductor Corp, CY7C1412AV18-167BZC Datasheet - Page 10

• Manufacturer Part Number: CY7C1412AV18-167BZC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1412AV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2668730

Document #: 38-05615 Rev. *C
Write Cycle Descriptions
Write Cycle Descriptions
Write Cycle Descriptions
BWS
BWS
BWS
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
L
0
H
H
H
H
0
L
/ NWS
0
BWS
0
H
H
H
H
H
H
H
H
L
L
L
L
L-H
L-H
K
–
–
BWS
1
BWS
1
H
H
H
L
L
/ NWS
H
H
H
H
H
H
H
H
L
L
L
L
L-H
L-H
K
–
–
2
1
BWS
During the Data portion of a Write sequence:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
During the Data portion of a Write sequence:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
H
H
H
H
H
H
H
H
L
L
L
L
L-H
L-H
K
(CY7C1410AV18 and CY7C1412AV18) (continued)
–
–
–
(CY7C1414AV18)
(CY7C1425AV18)
3
L-H
L-H
L-H
L-H
L-H
L-H
K
L-H
L-H
L-H
–
–
–
–
–
–
K
–
–
During the Data portion of a Write sequence:
CY7C1410AV18 − only the lower nibble (D
remain unaltered,
CY7C1412AV18 − only the lower byte (D
remain unaltered.
During the Data portion of a Write sequence:
CY7C1410AV18 − only the upper nibble (D
remain unaltered,
CY7C1412AV18 − only the upper byte (D
remain unaltered.
During the Data portion of a Write sequence:
CY7C1410AV18 − only the upper nibble (D
remain unaltered,
CY7C1412AV18 − only the upper byte (D
remain unaltered.
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L-H
L-H
L-H
L-H
L-H
L-H
K
–
–
–
–
–
[2, 8]
During the Data portion of a Write sequence, all four bytes (D
written into the device.
During the Data portion of a Write sequence, all four bytes (D
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
is written into the device. D
During the Data portion of a Write sequence, only the lower byte (D
is written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
During the Data portion of a Write sequence, only the byte (D
written into the device. D
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
Comments
[8:0]
[8:0]
[17:0]
[17:0]
[26:0]
[26:0]
Comments
[35:9]
[35:9]
and D
and D
[2, 8]
and D
and D
will remain unaltered.
will remain unaltered.
Comments
[8:0]
[17:9]
[17:9]
will remain unaltered.
will remain unaltered.
[3:0]
[7:4]
[7:4]
) is written into the device. D
[35:18]
[35:18]
[35:27]
[35:27]
) is written into the device. D
) is written into the device. D
) is written into the device. D
) is written into the device. D
) is written into the device. D
will remain unaltered.
will remain unaltered.
will remain unaltered.
will remain unaltered.
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Page 10 of 25
[35:0]
[35:0]
[17:9]
[17:9]
[26:18]
[26:18]
[35:27]
[35:27]
[17:9]
[8:0]
[8:0]
[7:4]
[3:0]
[3:0]
) are
) are
) is
) is
) is
) is
) is
) is
[8:0]
[8:0]
will
will
will
will
will
will
)
)
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