CY7C1412AV18-167BZC Cypress Semiconductor Corp, CY7C1412AV18-167BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1412AV18-167BZC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1412AV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2668730

Document #: 38-05615 Rev. *C
Application Example
Truth Table
Write Cycle Descriptions
Write Cycle:
Load address on the rising edge of K clock; input
write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes:
BWS
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
MASTER
charging symmetrically.
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
ASIC)
BUS
(CPU
0
or
L
L
L
/ NWS
CLKIN/CLKIN#
Delayed K#
DATA OUT
0
Delayed K
Source K#
Source K
DATA IN
[2, 3, 4, 5, 6, 7]
Address
BWS
BWS#
WPS#
RPS#
1
Operation
H
L
L
/ NWS
Vt
R
R
[1]
1
R = 50οηµσ
L-H
L-H
K
(CY7C1410AV18 and CY7C1412AV18)
–
D
A
L-H
K
–
–
Vt = Vddq/2
↑
R
P
#
S
represents rising edge.
W
SRAM #1
P
S
#
During the Data portion of a Write sequence:
CY7C1410AV18 − both nibbles (D
CY7C1412AV18 − both bytes (D
During the Data portion of a Write sequence:
CY7C1410AV18 − both nibbles (D
CY7C1412AV18 − both bytes (D
During the Data portion of a Write sequence:
CY7C1410AV18 − only the lower nibble (D
remain unaltered,
CY7C1412AV18 − only the lower byte (D
remain unaltered.
W
B
S
#
Stopped
C C#
L-H
L-H
L-H
K
CQ/CQ#
K
ZQ
K#
Q
R = 250οηµσ
RPS
X
H
X
L
[2, 8]
0
, NWS
WPS
X
H
X
L
1
[17:0]
[17:0]
, BWS
Comments
[7:0]
[7:0]
D(A + 0) at K(t) ↑
Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑
Q = High-Z
Previous State
D = X
D
A
) are written into the device.
) are written into the device.
) are written into the device,
) are written into the device,
0
, BWS
R
[8:0]
[3:0]
) is written into the device. D
1
Vt
Vt
, BWS
) is written into the device. D
DQ
R
P
S
#
W
SRAM #4
P
S
#
2
W
and BWS
B
S
#
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
C C#
3
D(A + 1) at K(t) ↑
D = X
Q = High-Z
Previous State
can be altered on different
CQ/CQ#
K
ZQ
K#
Q
Page 9 of 25
DQ
R = 250οηµσ
[17:9]
[7:4]
will
will
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