CY7C028V-25AC Cypress Semiconductor Corp, CY7C028V-25AC Datasheet
CY7C028V-25AC
Specifications of CY7C028V-25AC
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CY7C028V-25AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 16 organization (CY7C027V) • 64K x 16 organization (CY7C028V) • 32K x 18 organization (CY7C037V) • 64K x 18 organization (CY7C038V) • 0.35-micron CMOS for optimum speed/power • ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C027V/028V and CY7037V/038V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP (Top View CY7C028V (64K x 16) CY7C027V (32K x 16 CY7C027V/028V CY7C037V/038V ...
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Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [6] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND 16 ...
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... Power Applied .............................................– +125 C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................–0. Note: 7. Pulse width < 20 ns. 8. Industrial parts are available in CY7C028V and CY7C038V only. Description Chip Enable (CE is LOW when CE 0 Read/Write Enable Output Enable Address (A –A for 32K ...
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Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH (V =Min –4.0 mA Output LOW Voltage (V =Min Input HIGH Voltage IH V Input LOW Voltage IL ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [12 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [17] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t SEM Flag Update Pulse (OE or SEM) SOP t SEM Flag Write to Read Time SWRD ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [29,30 R/W NOTE 32 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [29,30 R/W DATA IN Notes: 25. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [41] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE 7FFE (FFFE for CY7C028V/38V R/W R INT L [41] t INS Left Side Clears INT ...
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... CY7C027V/37V, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/37V, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 42. A and A ,FFFF/FFFE for the CY7C028V/038V. 0L–15L 0R–15R 43. If BUSY =L, then no change. R 44. If BUSY =L, then no change. ...
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... Ordering Code 15 CY7C027V-15AC 20 CY7C027V-20AC 25 CY7C027V-25AC 64K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AC 20 CY7C028V-20AC CY7C028V-20AI 25 CY7C028V-25AC 32K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C037V-15AC 20 CY7C037V-20AC 25 CY7C037V-25AC 64K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C038V-15AC 20 ...
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... Package Diagram © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...