CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document #: 001-06984 Rev. *C
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
20. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
21. This part has a voltage regulator internally; t
22. For D0 data signal on CY7C1525AV18 device, t
23. These parameters are extrapolated from the input timing parameters (t
24. t
25. At any voltage and temperature t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
operated and outputs data with the output timings of that frequency range.
included in the t
[22]
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
KHKH
). These parameters are only guaranteed by design and are not tested in production.
V
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to K Clock Rise (RPS, WPS)
DDR Control Setup to Clock (K/K) Rise
(BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
DDR Control Hold after Clock (K/K) Rise
(BWS
D
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (C/C) Rise to High-Z (Active to High-Z)
Clock (C/C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
DD
[X:0]
[X:0]
[19, 20]
CHZ
(Typical) to the First Access
Hold after Clock (K/K) Rise
0
Setup to Clock (K/K) Rise
0
, BWS
, BWS
is less than t
POWER
1
1
, BWS
, BWS
SD
CLZ
is 0.5 ns for 200 MHz, and 250 MHz frequencies.
is the time that the power must be supplied above V
and t
2
2
, BWS
, BWS
CHZ
Description
[24, 25]
less than t
[23]
3
3
)
)
[23]
[21]
KHKH
AC Test Loads and
CO
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
.
[24, 25]
Waveforms. Transition is measured ± 100 mV from steady state voltage.
CY7C1510AV18, CY7C1525AV18
CY7C1512AV18, CY7C1514AV18
DD
minimum initially before initiating a read or write operation.
–0.45
–0.45
–0.30
–0.45
1024
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
1.55
1.55
Min Max Min Max Min Max
4.0
1.6
1.6
1.8
250 MHz
30
1
0
–
–
–
–
–
0.45
0.45
0.30
0.45
0.20
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.35
–0.45
1024
1.95
1.95
5.0
2.0
2.0
2.2
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
200 MHz
30
1
0
–
–
–
–
–
0.45
0.45
0.35
0.45
0.20
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.50
–0.50
–0.40
–0.50
1024
2.45
2.45
6.0
2.4
2.4
2.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
167 MHz
30
0
–
1
–
–
–
–
KC Var
Page 23 of 28
0.50
0.50
0.40
0.50
0.20
8.4
2.7
) is already
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Cycles
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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