IS24C02B-2ZLI-TR ISSI, Integrated Silicon Solution Inc, IS24C02B-2ZLI-TR Datasheet - Page 6

• Manufacturer Part Number: IS24C02B-2ZLI-TR
• Description: IC EEPROM 2KBIT 1MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02B-2ZLI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 400ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE OPERATIOn
IS24C01B/02B features
supports a bi-directional 2-wire bus transmission protocol
called I
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving devices as receivers. The bus is controlled
by Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C01B/02B is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
– During a data transfer, the SDA line must remain stable
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The EEPROM monitors the SDA and SCL
lines and will not respond until the Start condition is met.
6
IS24C01B IS24C02B
busy
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
2
C
TM
.
serial communication and
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C01B/02B contains a reset function in case the
2-wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C01B/02B will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following the
Stop signal if a no write operation is initiated; or c) Following
any internal write operation.
Integrated Silicon Solution, Inc. — www.issi.com
9/11/09
Rev. F