IS61LPS51236A-250B3LI-TR ISSI, Integrated Silicon Solution Inc, IS61LPS51236A-250B3LI-TR Datasheet - Page 11

• Manufacturer Part Number: IS61LPS51236A-250B3LI-TR
• Description: IC SRAM 18MBIT 250MHZ 165FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPS51236A-250B3LI-TR

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
TRUTH TABLE
NOTE:
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. N
02/12/2010
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
BWx, BWE, GW HIGH.
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
input data hold time.
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
(1-8)
(3CE option)
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
CE
CE
CE
CE
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
CE2
CE2
CE2
CE2
CE2
H
H
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
ADSP
ADSP
ADSP
ADSP ADSC
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
ADSC
ADSC
ADSC
ADSC
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
X
L
L
L
ADV
ADV
ADV
ADV
ADV WRITE
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
WRITE
WRITE
WRITE
WRITE
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
OE
OE
OE
OE
OE
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
D
D
Q
Q
D
D
Q
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