M25PX32-VMP6F NUMONYX, M25PX32-VMP6F Datasheet
M25PX32-VMP6F
Specifications of M25PX32-VMP6F
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M25PX32-VMP6F Summary of contents
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... More than 100 000 write cycles per sector More than 20 year data retention Packages – RoHS compliant Automotive Certified Parts Available March 2009 32-Mbit, dual I/O, 4-Kbyte subsector erase, Rev 10 M25PX32 VFQFPN8 (MP) 6 × SO8W (MW) 208 mils SO16 (MF) 300 mils TBGA24 (ZM) 6x8 mm www ...
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... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 2/ ...
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Read Status Register (RDSR 6.4.1 ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity Table 3. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9. Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10 ...
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... Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. BGA 6x8 24 ball ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Hold condition activation Figure 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9. Write Enable (WREN) instruction sequence Figure 10 ...
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... Description The M25PX32 Mbit ( serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX32 supports two new, high-performance dual input/output instructions: Dual Output Fast Read (DOFR) instruction used to read data MHz by using • both pin DQ1 and pin DQ0 as outputs Dual Input Fast Program (DIFP) instruction used to program data MHz by • ...
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... There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See section for package dimensions, and how to identify pin-1. Package mechanical V CC DQ1 M25PX32 Function M25PX32 DQ1 2 7 HOLD W ...
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... Figure 3. SO16 connections Note Don’t use. 2 See Section 11: Package Figure 4. BGA 6x8 24 ball ballout Note Connection 2 See Section 11: Package 8/68 M25PX32 HOLD DQ0 DQ1 8 9 W/V mechanical, and how to identify pin-1. mechanical. PP AI13721b ...
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Signal descriptions 2.1 Serial Data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) ...
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... If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register. See If V ...
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... Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in ensure that the M25PX32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 6. SPI modes supported CPOL CPHA ...
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... Subsector Erase, Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the ...
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... Protocol-related protections The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX32 features the following data protection mechanisms: Power On Reset and an internal timer (t • inadvertent changes while the power supply is outside the operating specification Program, Erase and Write Status Register instructions are checked that they consist of • ...
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... Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 and SPM2 The first software protected mode (SPM1) is managed by specific Lock Registers • ...
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... Status Register in a read-only mode. In this mode, the Block Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more details, see Section 6.5: Write Status Register Memory content Protected area All sectors Lower 63/64ths (63 sectors 62) ...
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Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is ...
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... Kbytes each) • 16384 pages (256 bytes each) • 64 OTP bytes located outside the main memory array • Each page can be individually programmed (bits are programmed from 1 to 0). The device is Subsector, Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Table 4. Memory organization Sector Subsector 1023 63 1008 1007 62 992 991 61 976 975 60 960 959 59 944 943 58 928 927 57 912 911 56 896 895 55 880 879 54 864 863 53 848 20/68 Address range Sector 3FF000h 3FFFFFh 52 3F0000h 3F0FFFh 3EF000h 3EFFFFh 51 3E0000h 3E0FFFh 3DF000h 3DFFFFh ...
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... Table 4. Memory organization (continued) Sector Subsector Address range 671 29F000h 41 656 290000h 655 28F000h 40 640 280000h 639 27F000h 39 624 270000h 623 26F000h 38 608 260000h 607 25F000h 37 592 250000h 591 24F000h 36 576 240000h 575 23F000h 35 560 230000h 559 22F000h 34 544 220000h 543 ...
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... Table 4. Memory organization (continued) Sector Subsector 319 19 304 303 18 288 287 17 272 271 16 256 255 15 240 239 14 224 223 13 208 207 12 192 191 11 176 175 10 160 159 9 144 22/68 Address range Sector 13F000h 13FFFFh 8 130000h 130FFFh 12F000h 12FFFFh 7 120000h 120FFFh 11F000h ...
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... High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected ...
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Table 5. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification RDSR Read Status Register WRSR Write Status Register WRLR Write to Lock Register RDLR Read Lock Register READ Read Data Bytes Read Data Bytes at higher ...
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Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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... The manufacturer identification is assigned by JEDEC, and has the value 20h. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (16h). The UID contains the length of the following data in the first byte (set to 10h) and 16 bytes of the optional Customized Factory Data (CFD) content ...
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Figure 11. Read Identification (RDID) instruction sequence and data-out sequence 28/68 ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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... When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits • starts from the top of the memory array (see When TB is set to ‘1’, the area protected by the Block Protect bits starts from the • ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction. ...
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... The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency f during the falling edge of Serial Clock (C) ...
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... Write, Program and Erase operations in this sector will not be ‘1’ executed. The memory contents will not be changed. Write, Program and Erase operations in this sector are ‘0’ executed and will modify the sector contents. ...
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... OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, f (C). The instruction sequence is shown in The address is automatically incremented to the next higher address after each byte of data is shifted out ...
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... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Figure 19. Page Program (PP) instruction sequence Instruction DQ0 Data byte ...
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Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. ...
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Figure 20. Dual Input Fast Program (DIFP) instruction sequence Instruction DQ0 High Impedance DQ1 ...
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... When bit 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and • cannot be programmed anymore. Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP memory array become read-only in a permanent way. ...
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Figure 21. Program OTP (POTP) instruction sequence Instruction DQ0 Data byte ...
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Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write ...
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Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device ...
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Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay of t • CC ...
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Figure 29. Power-up timing (max) Program, Erase and Write commands are rejected by the device Chip Selection not allowed V CC (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ...
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... Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device outside the ratings listed in cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 16. Capacitance Symbol C Input/output capacitance (DQ0/DQ1) IN/OUT C Input capacitance (other pins Sampled only, not 100% tested Table 17. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I ...
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Table 18. AC characteristics Test conditions specified in Symbol Alt. Parameter Clock frequency for the following instructions: DOFR, DIFP, FAST_READ SSE, SE, BE, DP, WREN, WRDI, RDID RDSR, WRSR, ROTP, PP, POTP, WRLR, RDLR, RDP f ...
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Table 18. AC characteristics (continued) Symbol Alt. t Write Status Register cycle time W Page Program cycle time (256 bytes) (7) t Page Program cycle time (n bytes) PP Program OTP cycle time (64 bytes) t Subsector Erase cycle time ...
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Figure 32. Write Protect Setup and Hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 High Impedance DQ1 Figure 33. Hold timing S C DQ1 DQ0 HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439c tHHCH AI13746 57/68 ...
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Figure 34. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN Figure 35. V PPH S C DQ0 V PPH V PP 58/68 tCLQV timing tVPPHSL tCH tCL LSB OUT tQLQH tQHQL End of command (identi ed ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Table 19. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package mechanical data Symbol Typ A 0. 0.65 A3 0.20 b 0.40 D 6.00 D1 5.75 D2 3.40 E 5.00 ...
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Figure 37. SO8W 8-lead plastic small outline, 208 mils body width, package outline Drawing is not to scale. Table 20. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Millimeters Symbol ...
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Figure 38. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 21. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Symbol Typ A ...
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Figure 39. TBGA, 6x8 mm, 24 ball package outline 63/68 ...
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Table 22. TBGA 6x8 mm 24-ball package dimensions MIN A A1 0.20 A2 Øb 0. balls aaa bbb ddd eee fff Control unit: mm ...
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... F = Tape and reel packing RoHS compliant Lithography B = 110nm, Fab.2 Diffusion Plant blank = 110 nm Automotive Grade ( Automotive –40 to 125 °C Part. Device tested with high reliability certified flow. blank = standard – °C device 1. Secure options are available upon customer request. M25PX32 – 65/68 ...
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... Numonyx strongly recommends the use of the Automotive Grade devices(AutoGrade 6 and Grade 3) for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. ...
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... Section 6.3: Read Identification (RDID) Modified the minimum value for t SHSL Minor text changes. Applied Numonyx branding. Corrected bulk erase specifications on the cover page; Added the following information regarding bulk erase: Avoid applying VPPH to the W/VPP pin during Bulk Erase. Added the TBGA package and accompanying informaiton. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...