CY62256NLL-55SNXIT Cypress Semiconductor Corp, CY62256NLL-55SNXIT Datasheet - Page 5

• Manufacturer Part Number: CY62256NLL-55SNXIT
• Description: IC SRAM 256KBIT 55NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62256NLL-55SNXIT

• Memory Size: 256K (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 50 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Rohs Compliant: YES
• Density: 256Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: SNC N
• Operating Temp Range: -40C to 85C
• Supply Current: 50mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-06511 Rev. *A
Switching Characteristics
Switching Waveforms
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Read Cycle No. 1
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
12. Device is continuously selected. OE, CE = V
13. WE is HIGH for Read cycle.
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
8. At any given temperature and voltage condition, t
9. t
Parameter
DATA OUT
ADDRESS
I
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
OL
HZOE
/I
OH
, t
and 100-pF load capacitance.
HZCE
[10, 11]
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
HZWE
[12, 13]
are specified with C
PREVIOUS DATA VALID
Description
Over the Operating Range
[8]
[8]
[8, 9]
[8, 9]
[8]
[8, 9]
L
IL
= 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
.
t
HZCE
OHA
is less than t
t
AA
LZCE
Min.
55
55
45
45
40
25
, t
5
5
5
0
0
0
0
5
HZOE
[7]
CY62256N-55
is less than t
t
RC
Max.
HZWE
55
55
25
20
20
55
20
LZOE
and t
, and t
SD
HZWE
.
is less than t
Min.
70
70
60
60
50
30
0
5
5
5
0
0
0
5
CY62256N-70
DATA VALID
LZWE
for any given device.
Max.
70
70
35
25
25
70
25
CY62256N
Page 5 of 13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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