CY62256NLL-55SNXIT Cypress Semiconductor Corp, CY62256NLL-55SNXIT Datasheet

no-image

CY62256NLL-55SNXIT

Manufacturer Part Number
CY62256NLL-55SNXIT
Description
IC SRAM 256KBIT 55NS 28SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr

Specifications of CY62256NLL-55SNXIT

Memory Size
256K (32K x 8)
Package / Case
28-SOIC (7.5mm Width)
Format - Memory
RAM
Memory Type
SRAM
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Access Time
55 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
50 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
5 V
Rohs Compliant
YES
Density
256Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
15b
Package Type
SNC N
Operating Temp Range
-40C to 85C
Supply Current
50mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Number Of Words
32K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62256NLL-55SNXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY62256NLL-55SNXIT
Quantity:
6 000
256K (32K × 8) Static RAM
Features
Cypress Semiconductor Corporation
Document Number: 001-06511 Rev. *D
Note
Logic Block Diagram
1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Temperature Ranges
High Speed: 55 ns
Voltage Range: 4.5 V to 5.5 V Operation
Low Active Power
Low Standby Power (LL version)
Easy Memory Expansion with CE and OE Features
TTL-Compatible Inputs and Outputs
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP,
28-pin (300-mil) Narrow SOIC, 28-pin TSOP-I, and 28-pin
Reverse TSOP-I Packages
Commercial: 0 °C to +70 °C
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
275 mW (max)
82.5 W (max)
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
198 Champion Court
INPUTBUFFER
32K x 8
DECODER
COLUMN
ARRA Y
POWER
DOWN
Functional Description
The CY62256N
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
by the address present on the address pins (A
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
0
through I/O
256K (32K × 8) Static RAM
San Jose
[1]
7
) is written into the memory location addressed
is a high performance CMOS static RAM
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
Revised January 4, 2011
CY62256N
0
408-943-2600
through A
14
).
[+] Feedback

Related parts for CY62256NLL-55SNXIT

CY62256NLL-55SNXIT Summary of contents

Page 1

... Note 1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document Number: 001-06511 Rev. *D 256K (32K × 8) Static RAM Functional Description The CY62256N organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers ...

Page 2

Contents Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... ...

Page 3

... Product Portfolio Product Min CY62256NLL Commercial 4.5 CY62256NLL Industrial CY62256NLL Automotive-A CY62256NLL Automotive-E Pin Configurations Figure 1. 28-pin DIP and Narrow SOIC Table 1. Pin Definitions Pin Number Type 1–10, 21, 23–26 Input 11–13, 15–19, Input/Output 27 Input/Control 20 Input/Control 22 Input/Control 14 Ground 28 Power Supply V Note 2 ...

Page 4

Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ........................................... –55 C to +125 C Supply voltage ...

Page 5

Thermal Resistance [7] Parameter Description  Thermal resistance JA (junction to ambient)  Thermal resistance JC (junction to case) R1 1800  OUTPUT OUTPUT R2 100 pF 990 INCLUDING INCLUDING JIG AND SCOPE (a) Data Retention ...

Page 6

... L 13. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. ...

Page 7

... Address valid prior to or coincident with CE transition LOW. 19. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. ...

Page 8

Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 25 t HZWE Notes 23. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is ...

Page 9

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0 25C A 0.4 0 0.0 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED ...

Page 10

Typical DC and AC Characteristics TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) Truth Table Inputs/Outputs High ...

Page 11

... Speed (ns) Ordering Code 55 CY62256NLL55SNXI CY62256NLL55ZXI CY62256NLL55ZXA CY62256NLL55SNXE CY62256NLL55ZXE 70 CY62256NLL70PXC CY62256NLL70SNXC CY62256NLL70ZRXI CY62256NLL70SNXA Do contact your local Cypress sales representative for availability of these parts Ordering Code Definitions CY 62 256 XXX X Document Number: 001-06511 Rev. *D ...

Page 12

Package Diagrams Figure 10. 28-pin (600-Mil) Molded DIP, 51-85017 Figure 11. 28-pin (300-mil) SNC (Narrow Body), 51-85092 Document Number: 001-06511 Rev. *D CY62256N 51-85017 *D 51-85092 *C Page [+] Feedback ...

Page 13

Figure 12. 28-pin TSOP I (8 × 13.4 mm), 51-85071 Figure 13. 28-pin TSOP I (8 × 13.4 mm), 51-85074 Document Number: 001-06511 Rev. *D CY62256N 51-85071 *H 51-85074-*F Page [+] Feedback ...

Page 14

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

Related keywords