CY62256NLL-55SNXIT Cypress Semiconductor Corp, CY62256NLL-55SNXIT Datasheet - Page 7

• Manufacturer Part Number: CY62256NLL-55SNXIT
• Description: IC SRAM 256KBIT 55NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62256NLL-55SNXIT

• Memory Size: 256K (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 50 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Rohs Compliant: YES
• Density: 256Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: SNC N
• Operating Temp Range: -40C to 85C
• Supply Current: 50mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Document Number: 001-06511 Rev. *D
Notes
17. WE is HIGH for Read cycle.
18. Address valid prior to or coincident with CE transition LOW.
19. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
20. Data I/O is high impedance if OE = V
21. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
22. During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
ADDRESS
DATA OUT
CURRENT
DATA I/O
DATA I/O
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
SUPPLY
CE
WE
WE
OE
V
CE
CE
OE
CC
NOTE
HIGH IMPEDANCE
22
t
PU
t
(continued)
LZCE
t
IH
SA
t
.
HZOE
Figure 7. Write Cycle No. 1 (WE Controlled)
Figure 8. Write Cycle No. 2 (CE Controlled)
t
t
ACE
LZOE
t
SA
50%
t
DOE
Figure 6. Read Cycle No. 2
t
AW
t
AW
t
RC
t
WC
t
WC
DATA
t
t
PWE
SD
DATA
t
IN
SCE
t
SD
VALID
[17, 18]
IN
DATA VALID
VALID
[19, 20, 21]
[19, 20, 21]
t
HD
t
HA
t
HA
t
HD
t
t
HZOE
HZCE
t
PD
50%
IMPEDANCE
CY62256N
HIGH
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