CY7C09159AV-12AC Cypress Semiconductor Corp, CY7C09159AV-12AC Datasheet
CY7C09159AV-12AC
Specifications of CY7C09159AV-12AC
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CY7C09159AV-12AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09159AV) — 16K x 9 organization (CY7C09169AV) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 83-MHz operation • ...
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... Functional Description The CY7C09159AV and CY7C09169AV are high-speed syn- chronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous ac- cess for reads and writes to any location in memory. ters on control, address, and data lines allow for minimal set- up and hold times ...
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... OEL 22 FT/PIPEL Note: 3. This pin is NC for CY7C09159AV. Selection Guide f (MHz) (Pipelined) MAX2 Max Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current I (mA) CC Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for (Both Ports CMOS Level) SB3 Document #: 38-06053 Rev ...
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... I/O –I Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current..................................................... >200 mA Operating Range Range +0.5V CC Commercial +0.5V CC [5] Industrial CY7C09159AV CY7C09169AV AND CE must be asserted MAX. for x9 devices). 8 Ambient Temperature +70 C 3.3V 300 mV – +85 C 3.3V ...
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... Ind. [6] Com’l. [5] MAX Ind. [6] Com’l. [5] Ind. [6] Com’l. [5] MAX Ind. Description Test Conditions MHz 3.3V CC AND CE 0 CY7C09159AV CY7C09169AV CY7C09159AV CY7C09169AV -9 -12 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.0 2.0 0.8 –10 10 –10 135 230 115 155 ...
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... AC Test Loads 3. 590 OUTPUT 435 (a) Normal Load (Load 1) Document #: 38-06053 Rev 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) CY7C09159AV CY7C09169AV 3. 590 OUTPUT 435 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) Page ...
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... Data Output Hold After Clock HIGH DC t Clock HIGH to Output High Z CKHZ t Clock HIGH to Output Low Z CKLZ Port to Port Delays t Write Port Clock High to Read Data Delay CWDD t Clock to Clock Set-up Time CCS Document #: 38-06053 Rev. *A CY7C09159AV CY7C09169AV CY7C09159AV -9 -12 Min. Max. Min. Max ...
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... DC CD1 CYC2 t CL2 A A n+1 t CD2 Q t CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09159AV CY7C09169AV n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ n+2 ...
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... CWDD Document #: 38-06053 Rev. *A CL2 CD2 HC CD2 [13, 14, 15, 16 MATCH CD1 CWDD . for the left port, which is being written to. IH CY7C09159AV CY7C09169AV CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not CWDD CCS CKHZ CD2 ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06053 Rev. *A [10, 17, 18, 19 n+1 n CD2 CKHZ Q n READ NO OPERATION [10, 17, 18, 19 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09159AV CY7C09169AV A A n+3 n CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Page CD2 Q n+3 Q n+4 ...
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... OUT OE Document #: 38-06053 Rev. *A [8, 10, 17, 18, 19 n+1 n CD1 CKHZ NO READ OPERATION [8, 10, 17, 18, 19 n OHZ READ CY7C09159AV CY7C09169AV n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ DC WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 ...
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... R/W and CNTRST = Document #: 38-06053 Rev. *A [20] t SAD t SCN t CD2 READ WITH COUNTER [20 n+1 READ WITH COUNTER . IH CY7C09159AV CY7C09169AV t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 COUNTER HOLD Q n+3 READ WITH ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06053 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09159AV CY7C09169AV [21, 22 n+2 n n+2 n+3 WRITE WITH COUNTER . IH A n+4 ...
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... HRST CNTRST t SD DATA IN DATA OUT COUNTER RESET Notes: 23 24. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06053 Rev. *A [10, 17, 23, 24 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09159AV CY7C09169AV n READ READ ADDRESS 1 ADDRESS n Page n ...
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... CNTRST I/O Mode Reset out( out( out( Increment out(n+ CY7C09159AV CY7C09169AV –I/O Operation 9 [28] Deselected [28] Deselected Write IN [28] Read Outputs Disabled Operation Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Ordering Information 8K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code 9 CY7C09159AV-9AC 12 CY7C09159AV-12AC 16K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code 9 CY7C09169AV-9AC 12 CY7C09169AV-12AC CY7C09169AV-12AI Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06053 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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... Document Title: CY7C09159AV/CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port SRAM Document Number: 38-06053 Issue REV. ECN NO. Date ** 110205 11/15/01 *A 122303 12/27/02 Document #: 38-06053 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00839 to 38-06053 RBI Power up requirements added to Maximum Ratings Information ...