CY7C09159AV-12AC Cypress Semiconductor Corp, CY7C09159AV-12AC Datasheet - Page 15

• Manufacturer Part Number: CY7C09159AV-12AC
• Description: IC SRAM 72KBIT 12NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09159AV-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 72K (8K x 9)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1177

Read/Write and Enable Operation
Address Counter Control Operation
Notes:
Document #: 38-06053 Rev. *A
25. “X” = “don’t care,” “H” = V
26. ADS, CNTEN, CNTRST = “don’t care.”
27. OE is an asynchronous input signal.
28. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
29. CE
30. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle.
31. Counter operation is independent of CE
Address
OE
A
H
X
X
X
X
X
X
L
n
0
and OE = V
Previous
Address
A
A
X
X
CLK
IL
n
n
; CE
X
1
and R/W = V
IH
CLK
, “L” = V
Inputs
CE
IL
H
X
L
L
L
ADS
.
IH
0
H
H
.
X
L
0
and CE
CNTEN
1
.
H
X
X
[25, 26, 27]
L
CE
X
H
H
H
L
[25, 29, 30, 31]
1
CNTRST
H
H
H
L
R/W
X
X
H
X
L
D
D
D
D
out(n+1)
I/O
out(0)
out(n)
out(n)
Outputs
I/O
High-Z
High-Z
High-Z
Increment
D
D
0
Mode
Reset
OUT
Load
Hold
–I/O
IN
9
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[28]
Operation
[28]
[28]
CY7C09159AV
CY7C09169AV
Operation
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