IDT71342LA20J IDT, Integrated Device Technology Inc, IDT71342LA20J Datasheet - Page 9

• Manufacturer Part Number: IDT71342LA20J
• Description: IC SRAM 32KBIT 20NS 52PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71342LA20J

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 71342LA20J

Timing Waveform of Write Cycle No. 2, CE Controlled Timing
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
9. To access SRAM, CE =V
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W W W W W CONTROLLED TIMING
CE or SEM
CE or SEM
ADDRESS
ADDRESS
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
DATA
for the required t
(Figure 2).
WR
DATA
DATA
is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
R/W
R/W
OUT
IN
OE
IN
(9)
(9)
DW
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
and SEM = V
EW
t
LZ
t
or t
AS
t
AS
IH
WP
(6)
. To access semaphore, CE = V
) of either CE or SEM = V
(6)
(4)
t
WZ
t
(7)
AW
IL
and R/W = V
t
AW
IH
t
t
WC
EW
and SEM = V
t
WP
6.42
(2)
t
9
WC
IL
(2)
.
IL
WP
. Either condition must be valid for the entire t
t
DW
or (t
WZ
t
DW
+ t
DW
Industrial and Commercial Temperature Ranges
t
) to allow the I/O drivers to turn off data to be placed on the bus
OW
t
WR
(3)
t
t
DH
WR
(3)
t
DH
EW
(1,5,8)
time.
(1, 5)
(4)
t
HZ
t
HZ
(7)
2721 drw 10
(7)
2721 drw 11
WP
.