CY7C09279V-6AXC Cypress Semiconductor Corp, CY7C09279V-6AXC Datasheet - Page 15

• Manufacturer Part Number: CY7C09279V-6AXC
• Description: IC SRAM 512KBIT 6.5NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09279V-6AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 512K (32K x 16)
• Speed: 6.5ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 512Kb
• Access Time (max): 15ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 53MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 320mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read/Write and Enable Operation
Address Counter Control Operation
Notes
Document #: 38-06056 Rev. *C
35. “X” = “Don’t Care”, “H” = V
36. ADS, CNTEN, CNTRST = “Don’t Care”.
37. OE is an asynchronous input signal.
38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
39. CE
40. Data shown for flow through mode; pipelined mode output is delayed by one cycle.
41. Counter operation is independent of CE
Address
OE
A
X
X
X
X
X
X
X
H
L
0
n
and OE = V
Previous
Address
IL
A
A
A
CLK
X
X
; CE
n
n
n
X
1
and R/W = V
IH
, “L” = V
CLK
Inputs
IL
CE
IH
.
H
X
L
L
L
.
0
0
and CE
ADS
H
H
H
X
L
1
.
CE
X
H
H
H
L
[35, 36, 37]
CNTEN
1
X
X
H
L
L
[35, 39, 40, 41]
CNTRST
R/W
H
X
X
X
L
H
H
H
H
L
D
D
D
D
D
out(n+1)
out(n+1)
I/O
out(0)
out(n)
out(n)
I/O
Outputs
High-Z
High-Z
High-Z
D
0
D
OUT
–I/O
IN
Increment
Increment
17
Mode
Reset
Load
Hold
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[35]
[38]
[38]
Operation
Operation
Page 15 of 19
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