MT48LC8M8A2TG-7E L:G TR Micron Technology Inc, MT48LC8M8A2TG-7E L:G TR Datasheet - Page 28

• Manufacturer Part Number: MT48LC8M8A2TG-7E L:G TR
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC8M8A2TG-7E L:G TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 16:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
READ-to-PRECHARGE
Note:
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL -1. This is shown in Figure 16 for each
possible CL; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL = -1. This is shown in Figure 17 on page 29 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
COMMAND
COMMAND
ADDRESS
ADDRESS
DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
COL n
T0
BANK,
COL n
READ
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
T2
T2
NOP
NOP
28
D
OUT
n
t
RP is met. Note that part of the row precharge time is
T3
T3
NOP
NOP
n + 1
D
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
OUT
n
TRANSITIONING DATA
PRECHARGE
PRECHARGE
T4
T4
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 3
D
n + 2
D
OUT
64Mb: x4, x8, x16 SDRAM
OUT
T6
T6
NOP
NOP
n + 3
D
©2000 Micron Technology, Inc. All rights reserved.
OUT
DON’T CARE
T7
NOP
Commands