MT48V8M16LFB4-8 XT:G TR Micron Technology Inc, MT48V8M16LFB4-8 XT:G TR Datasheet - Page 30

IC SDRAM 128MBIT 125MHZ 54VFBGA

MT48V8M16LFB4-8 XT:G TR

Manufacturer Part Number
MT48V8M16LFB4-8 XT:G TR
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48V8M16LFB4-8 XT:G TR

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-20°C ~ 75°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 15:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Random READ Accesses
Notes:
COMMAND
COMMAND
COMMAND
1. Each READ command may be to either bank. DQM is LOW.
2. BL = 1, 2, 4, 8, or full page (if BL > 1, the following READ interrupts the previous).
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
T0
BANK,
T0
BANK,
T0
BANK,
COL n
COL n
COL n
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
BANK,
BANK,
BANK,
READ
COL a
READ
COL a
READ
COL a
D
OUT
CL = 3
n
T2
T2
BANK,
BANK,
T2
READ
COL x
READ
COL x
READ
BANK,
COL x
30
D
D
OUT
OUT
n
a
T3
T3
T3
BANK,
COL m
BANK,
COL m
READ
READ
READ
BANK,
COL m
TRANSITIONING DATA
D
D
D
OUT
x
OUT
OUT
a
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
T4
T4
NOP
NOP
NOP
D
D
D
OUT
m
OUT
OUT
128Mb: x16, x32 Mobile SDRAM
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
DON’T CARE
T6
NOP
D
OUT
m
©2001 Micron Technology, Inc. All rights reserved.
READs

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