CY7C1361A-117AJC Cypress Semiconductor Corp, CY7C1361A-117AJC Datasheet - Page 7

• Manufacturer Part Number: CY7C1361A-117AJC
• Description: IC SRAM 9MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361A-117AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1120

Document #: 38-05259 Rev. *C
512K × 18 Pin Descriptions
(a) 6D, 7E, 6F, 7G, 6H,
1A, 7A, 1F, 7F, 1J, 7J,
5J, 1K, 6K, 2L, 4L, 7L,
1R, 5R, 7R, 1T, 4T, 6U
5K, 3L, 3M, 5M, 3N,
1B, 7B, 1C, 7C, 2D,
3D, 5D, 3E, 5E, 3F,
5F, 5G, 3H, 5H, 3K,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H, 3J,
6M, 2N, 7N, 1P, 6P,
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
4C, 2J, 4J, 6J, 4R
(not available for
X18 PBGA Pins
1M, 7M, 1U, 7U
7K, 6L, 6N, 7P
5N, 3P, 5P
PBGA)
4G
2B
4A
4B
3R
2U
3U
4U
5U
4F
7T
–
(for A Version only)
(b) 8, 9, 12, 13, 18,
40, 55, 60, 67, 71,
25, 28–30, 51–53,
56, 57, 66, 75, 78,
(a) 58, 59, 62, 63,
68, 69, 72, 73, 74
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
1–3, 6, 7, 14, 16,
38, 39, 42 for A
X18 QFP Pins
for BG and AJ
for BG and AJ
19, 22, 23, 24
79, 80, 95, 96
15, 41,65, 91
61, 70, 77
Version
version
version
76, 90
97
92
86
83
84
85
31
64
38
39
43
42
(continued)
MODE
ADSC
Name
ADSP
ADV
DQa
DQb
TMS
TDO
CE2
CE2
TCK
V
Pin
TDI
V
OE
V
NC
ZZ
CCQ
CC
SS
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Power
Ground
Output
Output
Supply
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input/
Static
Type
Input
Input
–
Chip Enable: This active HIGH input is used to enable the
device.
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
Output Enable: This active LOW asynchronous input
enables the data output drivers.
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to be
registered and a Read cycle is initiated using the new
address.
Address Status Controller: This active LOW input
causes device to be deselected or selected along with new
external address to be registered. A Read or Write cycle
is initiated depending upon Write control inputs.
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. An NC or HIGH on this pin
selects Interleaved Burst.
Sleep: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this
input has to be either LOW or NC (No Connect).
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set-up and hold times around the
rising edge of CLK.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not
available for A package version.
IEEE 1149.1 Test Output: LVTTL-level output. Not
available for A package version.
Core Power Supply: +3.3V –5% and +10%
Ground: GND.
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to V
Pin Description
CY7C1361A
CY7C1363A
CC
Page 7 of 27
or V
SS
.