CY7C09349AV-12AC Cypress Semiconductor Corp, CY7C09349AV-12AC Datasheet
CY7C09349AV-12AC
Specifications of CY7C09349AV-12AC
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CY7C09349AV-12AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09349AV) — organization (CY7C09359AV) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 83-MHz operation • ...
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... Functional Description The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times. In pipelined output mode, data is registered for decreased cycle time ...
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... Typical Operating Current I (mA) CC Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for (Both Ports CMOS Level) SB3 Shaded areas contain advance information. Note: 3. This pin is NC for CY7C09349AV. 100-Pin TQFP (Top View CY7C09359AV (8K x 18) ...
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... For read operations both Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial [4] +0.5V Industrial CC +0. CY7C09349AV CY7C09359AV AND CE must be asserted MAX –I/O ). 8/9L 15/17L Ambient Temperature +70 C 3.3V 300 mV – ...
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... CC Ind. Com’ [4] IH MAX Ind. Test Conditions MHz 3.3V CC AND CE must be asserted to their active states ( CY7C09349AV CY7C09359AV CY7C09349AV CY7C09359AV -9 -12 Typ. Max. Min. Typ. Max. Unit 2.4 0.4 0.4 2.0 0.8 0.8 10 –10 10 135 230 115 180 mA ...
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... AC Test Loads 3. 590 OUTPUT 435 (a) Normal Load (Load 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) 6 CY7C09349AV CY7C09359AV 3. 590 OUTPUT 435 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ...
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... Data Output Hold After Clock HIGH DC t Clock HIGH to Output High Z CKHZ t Clock HIGH to Output Low Z CKLZ Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-up Time CCS CY7C09349AV CY7C09359AV -9 Min. Max. Min CY7C09349AV CY7C09359AV -12 Max. Unit 33 MHz 50 MHz ...
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... DC CD1 CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09349AV CY7C09359AV n+3 t CKHZ Q Q n+1 n OHZ OLZ n n+1 t OHZ ...
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... CD1 CWDD CD2 CD2 [12, 13, 14, 15] NO MATCH t CD1 MATCH t CWDD VALID , R/W, CNTEN, and CNTRST = for the left port, which is being written to CY7C09349AV CY7C09359AV CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ CKLZ NO t CD1 VALID >maximum specified, then data is not valid ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. [9, 16, 17, 18 n+1 n CD2 CKHZ Q n READ NO OPERATION [9, 16, 17, 18 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH 10 CY7C09349AV CY7C09359AV A A n+3 n CD2 CKLZ WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Q n+3 ...
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... SA HA DATA IN t CD1 DATA OUT OE [7, 9, 17, 18 n+1 n CD1 Q n CKHZ NO READ OPERATION [7, 9, 16, 17, 18 n OHZ READ WRITE 11 CY7C09349AV CY7C09359AV n+2 n+3 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n+4 n+5 n CD1 Q n CKLZ DC READ t CD1 t CD1 ...
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... CE , R/W and CNTRST = [19] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER [19 n+1 READ WITH COUNTER . IH 12 CY7C09349AV CY7C09359AV t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 READ COUNTER HOLD WITH COUNTER Q n+3 ...
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... CE and CNTRST = 21. The “Internal Address” is equal to the “External Address” when ADS = n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = CY7C09349AV CY7C09359AV [20, 21 n+2 n n+3 n+4 WRITE WITH COUNTER . IH n+4 ...
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... SRST HRST CNTRST t SD DATA D IN DATA OUT COUNTER RESET Notes: 22 UB, and 23. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset WRITE READ ADDRESS 0 ADDRESS 0 14 CY7C09349AV CY7C09359AV n READ READ ADDRESS 1 ADDRESS n n ...
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... CNTEN CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09349AV CY7C09359AV Operation 17 [27] Deselected [27] Deselected Write [27] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack CY7C09349AV CY7C09359AV Operating Range Commercial Commercial Operating Range Commercial Commercial Industrial 51-85048-B ...