RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 40

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.2
10.3
il.
40
Table 16. Read Configuration Register (Sheet 1 of 2)
Synchronous Burst-Mode Read
Since asynchronous page mode is the default read mode following a device power-up or reset, the
appropriate bits in the RCR must be set before synchronous burst mode reads of the flash memory
can occur. See
after configuring the RCR, it is not necessary to issue the Read Array command (0xFF) before
performing a synchronous burst-mode read. However, to perform a synchronous burst-mode read
after executing any other device operation (e.g., a write operation), it is necessary to issue the Read
Array command before performing a synchronous burst-mode read of the flash memory.
To perform a synchronous burst-mode read, an address is driven onto A[A
and OE# are asserted. WE# and RST# must be de-asserted. ADV# is asserted, then de-asserted to
latch the address. Alternatively, ADV# can remain asserted throughout the burst access, in which
case, the address is latched on the next valid CLK edge.
In synchronous burst mode, one or two of the 16 eight-word groups are “sensed” simultaneously
from the flash memory and loaded into an internal page buffer. After the initial access delay, the
first word is output from the data buffer on the next valid CLK edge. Subsequent buffer data is
output on valid CLK edges. Synchronous burst-mode reads can only step through the data buffer
once, and can only do so in a sequential manner; starting from the address latched at the beginning
of the burst cycle (see
The device supports 8- or 16- word bursts. However, by controlling certain control signals, such as
CE# and/or OE#, the device can output less than 8/16-words of synchronous data. A burst-mode
read can be used to access register information. When a burst-mode read is performed on a register,
only one word is loaded into the data buffer. In burst mode, the address is latched by either the
rising edge of ADV# or the next valid edge of CLK with ADV# low, whichever occurs first.
Read Configuration Register
The Read Configuration Register (RCR) is used to select the read mode (synchronous or
asynchronous), and it defines the synchronous burst characteristics of the device. To modify the
RCR settings, write the RCR command to the device (see
page
RCR contents can be examined by writing the Read Identifier command to the device. See
14.2, “Read Device Identifier” on page
sections describe each RCR bit in detail.
Read Configuration Register (RCR)
Mode
Read
RM
Bit
15
15
35).
Read Mode (RM)
14
Latency Count
Section 10.3, “Read Configuration Register” on page 40
13
LC[3:0]
Name
Section 7.1, “Read Operations” on page
12
11
Polarity
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
WAIT
WP
10
57). The RCR Register is shown in
Hold
Data
DH
9
Delay
WAIT
WD
8
Burst
Seq
BS
7
Section 9.0, “Bus Operations” on
Edge
CLK
CE
24).
Description
6
RES
R
5
for details. Immediately
MAX
Table
RES
R
4
:A
16. The following
MIN
RES
Default Value = 0xFFC7
R
3
], and CE#
Datasheet
2
Burst Length
Section
BL[2:0]
1
0