RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 50

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
12.0
12.1
12.2
50
Erase Mode
Flash erasing is performed on a block basis; therefore, only one block can be erased at a time.
When a block is erased, all bits within that block will read as a logic level one. To determine the
status of a Block Erase, poll the status register and analyze the bits. The following section describes
Block Erase operations in detail.
Block Erase
Block Erase operations are initiated by writing the Block Erase command to the address of the
block to be erased (refer to
Block Erase Confirm command written to the address of the block to be erased. If the device is
placed in standby (CE# de-asserted) during an erase operation, the device will continue to erase the
block until the erase operation is completed before entering standby. V
and the block must be unlocked (see
must remain at a valid level, and WP# must remain unchanged while in erase suspend.
During a Block Erase, the Write State Machine executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block are erased. Erasing the flash memory
changes array data from “zeros” to “ones.”
Status Register bit SR7 indicates Block Erase status while the sequence executes. If Status Register
bit SR5 is set after erase completion, this indicates an erase failure. If SR3 is set, this indicates that
the Write State Machine could not perform the erase operation because V
acceptable limits. If SR1 is set, the erase operation attempted to erase a locked block, causing the
operation to abort. CE# or OE# must be toggled to update Status Register contents.
After examining the status register, it should be cleared using the Clear Status Register command
before issuing a new command. Any valid command can follow, once the block erase operation has
completed.
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows
data to be accessed from memory locations other than the one being erased. The Erase Suspend
command can be issued to any device address within the block. A block erase operation can be
suspended to perform either a word program or a read operation within any block, except the block
that is in an erase suspend state (see
When a block erase operation is executing, issuing the Erase Suspend command requests the Write
State Machine to suspend the erase algorithm at predetermined points. An erase operation cannot
be nested within another erase suspend operation. Block erase is suspended when Status Register
bits SR[7,6] are set. Suspend latency is specified in
Operation Performance” on page
Block erase cannot resume until program operations initiated during erase suspend complete. Read
Array, Read Status Register, Read Identifier, CFI Query, and Program Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase
Resume, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
Section 9.2, “Device Commands” on page
31.
Figure 30, “Erase Suspend/Resume Flowchart” on page
Figure 29, “Block Erase Flowchart” on page
Section 7.3, “Block Erase and Program
37). This is followed by the
PEN
PEN
must be above V
was outside of its
74). Also, V
Datasheet
PENLK
75).
PEN