M95010-WMN6P STMicroelectronics, M95010-WMN6P Datasheet - Page 13

IC EEPROM 1KBIT 10MHZ 8SOIC

M95010-WMN6P

Manufacturer Part Number
M95010-WMN6P
Description
IC EEPROM 1KBIT 10MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheets

Specifications of M95010-WMN6P

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Memory Configuration
128 X 8
Interface Type
Serial, SPI
Clock Frequency
10MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SO
No. Of Pins
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8600-5
M95010-WMN6P

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M95010-WMN6P
Manufacturer:
ST
0
M95040, M95020, M95010
4
4.1
4.2
Operating features
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5
with Serial Clock (C) being low.
Figure 5.
Status register
Figure 6
register contains a number of control bits and status bits, as shown in
description of the Status register bits, see
HOLD
C
also shows what happens if the rising and falling edges are not timed to coincide
shows the position of the Status register in the control logic of the device. This
Hold condition activation
Doc ID 6512 Rev 8
Condition
Hold
Section 6.3: Read Status Register
Figure
5).
Condition
Hold
Table
Operating features
5. For a detailed
(RDSR).
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