CY7C1263V18-375BZXC Cypress Semiconductor Corp, CY7C1263V18-375BZXC Datasheet

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... Double Data Rate (DDR) interfaces. Each address location (CY7C1261V18), 9-bit words (CY7C1276V18), 18-bit words (CY7C1263V18), or 36-bit words (CY7C1265V18) that burst [1] sequentially into or out of the device. Because data can be trans- DD ferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simpli- fying system design by eliminating bus “ ...

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... D [8:0] 9 Address Register A (19: CLK K Gen. DOFF V REF WPS Control Logic BWS [0] Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write Write ...

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... Logic Block Diagram (CY7C1263V18) D [17:0] 18 Address Register A (18: CLK K Gen. DOFF V REF WPS Control Logic BWS [1:0] Logic Block Diagram (CY7C1265V18) D [35:0] 36 Address Register A (17: CLK K Gen. DOFF V REF WPS Control Logic BWS [3:0] Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 ...

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... DOFF REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 CY7C1261V18 ( NC/144M NC/144M WPS NWS NC/288M K NWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD CY7C1276V18 ( WPS NC K NC/144M A NC/288M K BWS ...

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... D30 D22 Q22 DOFF REF DDQ J D31 Q31 D23 K Q32 D32 Q23 L Q33 Q24 D24 M Q34 D33 D25 N D34 D26 Q25 P Q35 D35 Q26 R TDO TCK A Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 CY7C1263V18 ( NC/288M WPS BWS BWS DDQ ...

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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1261V18 arrays each for CY7C1276V18 arrays each of 512K x 18) for CY7C1263V18 and arrays each of 256K x 36) for are needed to access the entire memory array of CY7C1261V18 and CY7C1276V18, 19 address inputs for CY7C1263V18 and 18 address inputs for CY7C1265V18 ...

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... V Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Pin Description 24. 24. output impedance are set to 0.2 x RQ, where [x:0] Switching Character- Switching Character- Page [+] Feedback ...

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... CY7C1261V18, CY7C1276V18, and CY7C1265V18. Read Operations The CY7C1263V18 is organized internally as 4 arrays of 512K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The addresses presented to address inputs are stored in the Read address register ...

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... Depth Expansion The CY7C1263V18 has a Port Select input for each port. This enables easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected ...

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... DATA OUT Address RPS BUS MASTER WPS (CPU or ASIC) BWS CLKIN/CLKIN Source K Source K Truth Table The truth table for the CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 follows. Operation K RPS WPS [8] Write Cycle: L Load address on the rising edge of K; input write data on two consecutive K and K rising edges ...

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... Write Cycle Descriptions The write cycle descriptions table for CY7C1261V18 and CY7C1263V18 follows. BWS / BWS / NWS NWS L–H – During the data portion of a write sequence: CY7C1261V18 − both nibbles (D CY7C1263V18 − both bytes ( – L-H During the data portion of a write sequence: CY7C1261V18 − ...

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... H L– – Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 [2, 10] K Comments – During the data portion of a write sequence, all four bytes (D into the device. L–H During the data portion of a write sequence, all four bytes (D into the device. ...

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... TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in page 16 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP Controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- ...

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... These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in 13. Overshoot: V (AC) < 0.3V (pulse width less than t IH DDQ 14. All voltage refer to Ground. Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 0 Bypass Register Instruction Register ...

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... TMS Hold after TCK Clock Rise TMSH t TDI Hold after Clock Rise TDIH t Capture Hold after Clock Rise CH Output Times t TCK Clock LOW to TDO Valid TDOV t TCK Clock LOW to TDO Invalid TDOX Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Description Min Max Unit MHz ...

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... Test Data Out TDO Notes 15. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 16. Test conditions are specified using the load in TAP AC test conditions. t Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 [16] ALL INPUT PULSES 50Ω 1. ...

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... Do Not Use: This instruction is reserved for future use. 110 Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Description CY7C1265V18 000 Version number. of SRAM. 00000110100 ...

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... Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... Clock Start (Clock Starts after DDQ is Stable DDQ DDQ Stable (< + 0.1V DC per 50 ns) DOFF Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ ...

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... Inputs Static 400 MHz Test Conditions (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Ambient [17 DDQ 1.8 ± 0.1V 1. Min Typ Max Unit 1 ...

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... R = 50Ω REF OUTPUT = 50Ω Device 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Max Unit 165 FBGA Unit Package 16.25 °C/W 2.91 °C/W [22] ALL INPUT PULSES 1.25V 0.75V 0.25V Slew Rate = 2 V/ns = 0.75V 250Ω ...

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... V – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t KHKH AC Test Loads and Waveforms on page and t less than t . CLZ CHZ CO CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 375 MHz 333 MHz 300 MHz Unit 1 – 1 – 1 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 READ WRITE NOP 5 ...

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... CY7C1261V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1276V18-375BZC CY7C1263V18-375BZC CY7C1265V18-375BZC CY7C1261V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1276V18-375BZXC CY7C1263V18-375BZXC CY7C1265V18-375BZXC CY7C1261V18-375BZI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1276V18-375BZI CY7C1263V18-375BZI CY7C1265V18-375BZI CY7C1261V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free ...

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... Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1276V18-300BZI CY7C1263V18-300BZI CY7C1265V18-300BZI CY7C1261V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1276V18-300BZXI CY7C1263V18-300BZXI CY7C1265V18-300BZXI Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 Package Type Commercial Commercial Operating Range Industrial Industrial Page [+] Feedback ...

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... Package Diagram Figure 5. 165-Ball FBGA ( 1.40 mm), 51-85195 Document Number: 001-06366 Rev. *E CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 51-85195-*A Page [+] Feedback ...

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... Document History Page Document Title: CY7C1261V18/CY7C1276V18/CY7C1263V18/CY7C1265V18, 36-Mbit QDR™-II+ SRAM 4-Word Burst Ar- chitecture (2.5 Cycle Read Latency) Document Number: 001-06366 SUBMISSION REV. ECN NO. DATE ** 425689 See ECN *A 461639 See ECN *B 497628 See ECN *C 1072841 See ECN *D 2198506 See ECN *E 2560835 09/02/08 © ...