CY7C1263V18-375BZXC Cypress Semiconductor Corp, CY7C1263V18-375BZXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1263V18-375BZXC
• Description: IC SRAM 36MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1263V18-375BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (4M x 8)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Example
Figure 1
Truth Table
The truth table for the CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 follows.
Notes
Document Number: 001-06366 Rev. *E
Write Cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
Read Cycle:
(2.5 cycle Latency)
Load address on the
rising edge of K; wait
two and half cycle;
read data on two
consecutive K and K
rising edges.
NOP: No Operation
Standby: Clock
Stopped
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represent the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively,
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores
BUS MASTER
(CPU or ASIC)
succeeding the “t” clock cycle.
symmetrically.
the second read or write request.
Operation
shows the use of four QDR-II+ SRAMs in an application.
CLKIN/CLKIN
DATA OUT
Source K
Source K
DATA IN
Address
WPS
BWS
RPS
L-H
L-H
L-H
Stopped X
K
Vt
R
H
L
H
RPS WPS
[9]
[8]
D
A
L
X
H
X
RPS WPS BWS
[9]
↑
SRAM #1
represents rising edge.
D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 4) ↑
D = X
Q = High-Z
Previous State
Figure 1. Application Example
DQ
CQ/CQ
K
ZQ
Q
K
D = X
Q = High-Z
Previous State
RQ = 250ohms
DQ
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
D
A
D = X
Q = High-Z
Previous State
R
R
Vt
Vt
RPS WPS BWS
R = 50ohms, Vt = V
SRAM #4
DQ
[2, 3, 4, 5, 6, 7]
CQ/CQ
D = X
Q = High-Z
Previous State
K
DDQ
ZQ
Q
K
/2
RQ = 250ohms
DQ
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