M25P80-VMN3P/4 NUMONYX, M25P80-VMN3P/4 Datasheet - Page 36

• Manufacturer Part Number: M25P80-VMN3P/4
• Description: IC SRL FLASH 8MBIT 3V SO8 AUTO
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMN3P/4

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during Power-up, a Power-On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the POR threshold value, V
respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
t
correct operation of the device is not guaranteed if, by this time, V
No Write Status Register, Program or Erase instructions should be sent until the later
occurance of:
These values are specified in
If the delay, t
selected for READ instructions even if the t
At Power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
device in a system should have the V
package pins. (Generally, this capacitor is of the order of 100 nF.)
At Power-down, when V
(POR) threshold value, V
any instruction. (The designer needs to be aware that if a Power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption can result.)
PUW
V
V
t
t
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
PUW
VSL
has elapsed after the moment that V
CC
SS
(min) at Power-up, and then for a further delay of t
at Power-down
after V
after V
VSL
CC
, has elapsed, after V
CC
passed the V
passed the V
CC
WI
, all operations are disabled and the device does not respond to
drops from the operating voltage, to below the Power On Reset
Table
CC
WI
CC
) until V
WI
Section 3: SPI
– all operations are disabled, and the device does not
(min) level
8.
threshold
CC
CC
rail decoupled by a suitable capacitor close to the
has risen above V
CC
CC
PUW
reaches the correct value:
rises above the V
delay is not yet fully elapsed.
modes.
CC
VSL
(min), the device can be
WI
CC
threshold. However, the
is still below V
CC
CC
feed. Each
CC
is less
(min).