NAND01GR3B2BZA6E NUMONYX, NAND01GR3B2BZA6E Datasheet
NAND01GR3B2BZA6E
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NAND01GR3B2BZA6E Summary of contents
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... Development tools – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models NAND01GR3B2B, NAND01GW3B2B NAND01GR4B2B NAND02GR3B2C, NAND02GW3B2C NAND02GR4B2C, NAND02GW4B2C Rev 6 NAND01G-B2B NAND02G-B2C Not For New Design TSOP48 FBGA Root part number (1) , NAND01GW4B2B (1) www.numonyx.com 1/61 1 ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Inputs/outputs (I/O0-I/O7 3.2 Inputs/outputs (I/O8-I/O15 3.3 Address Latch Enable (AL 3.4 Command Latch Enable (CL 3.5 Chip Enable ( 3.6 Read Enable ( 3.7 Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB ...
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... Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.1 8.6.2 9 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 40 10 Maximum ratings ...
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Contents 12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND01G-B2B, NAND02G-B2C List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. VFBGA63 connections (top view through package Figure 5. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. ...
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... Serial number (unique identifier) option, which allows each device to be uniquely identified. These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For more details about them, refer to the nearest Numonyx sales office. Description 7/61 ...
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... Description For information on how to order these options refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2: Product Table 2. Product description Reference Part number Density NAND01GR3B2B NAND01GW3B2B ...
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... Logic diagram 1. x16 organization only available for MCP. P/E/R controller, high voltage generator I/O8-I/O15, x16 E R I/O0-I/O7, x8/x16 W NAND01G-B2B NAND02G-B2C NAND flash memory array Page buffer Cache register Y decoder I/O buffers & latches I/O0-I/O7, x8/x16 I/O8-I/O15, x16 RB AI13101 Description AI12799 9/61 ...
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Description Table 3. Signal names Signal I/O8-15 Data input/outputs for x16 devices Data input/outputs, address inputs, or command inputs I/O0-7 for x8 and x16 devices AL Address Latch Enable CL Command Latch Enable E Chip Enable R Read Enable RB ...
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NAND01G-B2B, NAND02G-B2C Figure 3. TSOP48 connections 1. Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices NAND01GW3B2B 37 NAND02GW3B2C ...
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Description Figure 4. VFBGA63 connections (top view through package Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices. 12/61 ...
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... Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification ...
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... Memory array organization Figure 5. Memory array organization x8 DEVICES Block = 64 pages Page = 2112 bytes (2,048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2,048 bytes 14/61 Block Page 8 bits 64 bytes 64 8 bits bytes NAND01G-B2B, NAND02G-B2C x16 DEVICES Block = 64 pages Page = 1056 words (1024 + 32) ...
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... When CL is High, the inputs are latched on the rising edge of Write Enable. 3.5 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V High while the device is busy, the device remains selected and does not go into standby IH mode ...
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... 3.10 V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 22 and Table power-transitions. Each device in a system should have V widths should be sufficient to carry the required program and erase currents ...
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... Data output Data output bus operations are used to read: the data in the memory array, the status register, the lock status, the electronic signature and the unique identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low ...
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... Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. ...
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NAND01G-B2B, NAND02G-B2C Table 7. Address insertion, x16 devices I/O8- Bus (1) cycle I/O15 th( Any additional address input cycles will be ignored. 2. The fifth ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations The following section gives the details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, see Once a Read command is issued two types of operations are available: random read and page read ...
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Device operations Figure 6. Read operations I/O Address input 00h Command code 1. Highest address depends on device density. 22/61 tBLBH1 30h Data output (sequentially) Command Busy code NAND01G-B2B, NAND02G-B2C ai08657b ...
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NAND01G-B2B, NAND02G-B2C Figure 7. Random data output during sequential data output tBLBH1 (Read Busy time Address 30h I/O 00h inputs Cmd Cmd code code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main area Busy 05h Data ...
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Device operations 6.2 Cache read The cache read operation is used to improve the read throughput by reading data using the cache register. As soon as the user starts to read one page, the device automatically loads the next page ...
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... NAND01G-B2B, NAND02G-B2C 6.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however the device does support random input within a page recommended to address pages sequentially within a given block. The memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed ...
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Device operations Figure 9. Page program operation RB I/O 80h Page Program Setup Code Figure 10. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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... The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
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Device operations Figure 11. Copy back program Source I/O 00h Add Inputs Read Code (Read Busy time) RB Figure 12. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) ...
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... Once the data is loaded into the page buffer the P/E/R controller programs the data into the memory array. As soon as the cache registers are empty (after t Cache Program command can be issued, while the internal programming is still executing. Once the program operation has started the status register can be read using the Read Status Register command. During cache program operations SR5 can be read to find out whether the internal programming is ongoing (SR5 = ‘ ...
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... The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. ...
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NAND01G-B2B, NAND02G-B2C 6.8 Read status register The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status ...
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... The error bit is used to identify if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. The error bit SR0 cache program operation, indicates a failure on page N. ...
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NAND01G-B2B, NAND02G-B2C 6.9 Read electronic signature The device contains a manufacturer code and device code. To read these codes three steps are required: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One bus write ...
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Device operations Table 16. Electronic signature byte/word 4 I/O I/O1-I/O0 I/O2 I/O7, I/O3 I/O5-I/O4 I/O6 34/61 Definition Page size (without spare area) Spare area size (byte/512-byte) Minimum sequential access time Block size (without spare area) Organization NAND01G-B2B, NAND02G-B2C Value Description ...
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... It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended to keep down. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever V is below V ...
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... To help integrate a NAND memory into an application, Numonyx can provide a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. ...
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NAND01G-B2B, NAND02G-B2C Table 17. NAND flash failure modes Operation Erase Program Read Figure 15. Bad block management flowchart Figure 16. Garbage collection Valid page Invalid page Procedure Block replacement Block replacement or ECC START Block Address = Block 0 Increment ...
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... For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details. 38/61 NAND01G-B2B, NAND02G-B2C ...
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NAND01G-B2B, NAND02G-B2C Figure 17. Error detection 8.6 Hardware simulation models 8.6.1 Behavioral simulation models Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior ...
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Program and erase times and endurance cycles 9 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 18. Table 18. Program, erase times and program ...
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NAND01G-B2B, NAND02G-B2C 10 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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DC and AC parameters 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from ...
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NAND01G-B2B, NAND02G-B2C Figure 18. Equivalent testing circuit for AC characteristics measurement V DD NAND flash C L GND GND DC and AC parameters 2R ref 2R ref Ai11085 43/61 ...
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DC and AC parameters Table 22. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage ...
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NAND01G-B2B, NAND02G-B2C Table 24. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable High ALLWH t ALS t Address Latch High to Write Enable High ALHWH Command Latch High to Write Enable ...
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DC and AC parameters Table 25. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t ...
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NAND01G-B2B, NAND02G-B2C Figure 19. Command Latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 20. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH ...
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DC and AC parameters Figure 21. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. Data in last is 2112 in x8 devices and 1056 in x16 devices. Figure 22. Sequential ...
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NAND01G-B2B, NAND02G-B2C Figure 23. Read status register AC waveforms CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 24. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to ...
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DC and AC parameters Figure 25. Page read operation AC waveforms CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code 1. A fifth address cycle is ...
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NAND01G-B2B, NAND02G-B2C Figure 26. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code 1. A fifth address cycle is required for 2-Gbit devices ...
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DC and AC parameters Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command 1. Address cycle 3 is required for 2-Gbit ...
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NAND01G-B2B, NAND02G-B2C Figure 29. Program/erase enable waveforms W tVHWH WP RB I/O Figure 30. Program/erase disable waveforms W tVLWH WP High RB I/O 11.1 Ready/Busy signal electrical characteristics Figure 32, Figure 31 signal. The value required for the resistor R ...
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DC and AC parameters Figure 31. Ready/Busy AC waveform Figure 32. Ready/Busy load circuit Figure 33. Resistor value versus waveform timings for Ready/Busy signal 25°C. 54/61 ready busy ...
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... NAND01G-B2B, NAND02G-B2C 11.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee hardware protection during power transitions as shown in the below IL figure. Figure 34. Data protection Nominal Range ...
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... Package mechanical 12 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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NAND01G-B2B, NAND02G-B2C Figure 36. VFBGA63 9 +15, 0.80 mm pitch, package outline Drawing is not to scale Table 27. VFBGA63 9 ...
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Package mechanical Figure 37. VFBGA63 1. +15, 0.80 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale Table 28. VFBGA63 ...
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... MCP products. 2. For NAND02G-B2C devices only. 3. For NAND01G-B2B devices only. Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. Ordering information NAND02GR3B2C ...
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... WHBH2 BLBH5 program. Alt. symbol for BLBH4 operations. 5 Applied Numonyx branding. Document status upgraded to not for new design. Modified Figure 31: Ready/Busy AC value versus waveform timings for Ready/Busy signal of the VFBGA63 package in 6 packages removed and replaced by references to RoHS compliance. Removed temperature range °C in information scheme ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...