EPC1213LC20 Altera, EPC1213LC20 Datasheet - Page 26

• Manufacturer Part Number: EPC1213LC20
• Description: IC CONFIG DEVICE 212KBIT 20-PLCC
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC1213LC20

• Programmable Type: OTP
• Memory Size: 212kb
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-PLCC
• For Use With: PLMJ1213 - PROGRAMMER ADAPTER 20 PIN J-LEAD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2188-5

1–24
Table 1–9. External Flash Interface Pins (Part 3 of 3)
Table 1–10. JTAG Interface Pins and Other Required Controller Pins
Configuration Handbook (Complete Two-Volume Set)
BYTE#
Notes to
(1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections
(2) For more information, refer to the Process Change Notification
TDI
TDO
TCK
TMS
PGM[2..0]
EXCLK
PORSEL
TM0
TM1
Pin Name
Pin Name
from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the
two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE# pin from controller to F-WE# pin from the
flash memory).
Enhanced Configuration Devices
Table
1–9:
Pin Type
Pin Type
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
and
Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16
Flash byte-enable pin and is only available for enhanced configuration devices in
the 100-pin PQFP package.
This pin must be connected to V
external flash interface (the controller uses the flash in 16-bit mode). For Intel
flash-based EPC device, this pin is connected to the V
internally. Therefore, BYTE# must be connected directly to V
pull-up resistor.
JTAG data input pin.
Connect this pin to V
JTAG data output pin.
Do not connect this pin if the JTAG circuitry is not used (leave floating).
JTAG clock pin.
Connect this pin to GND if the JTAG circuitry is not used.
JTAG mode select pin.
Connect this pin to V
These three input pins select one of the eight pages of configuration data to
configure the FPGAs in the system.
Connect these pins on the board to select the page specified in the Quartus II
software when generating the enhanced configuration device POF. PGM[2] is the
MSB. The default selection is page 0; PGM[2..0]=000. These pins must not be
left floating.
Optional external clock input pin that can be used to generate the configuration
clock (DCLK).
When an external clock source is not used, connect this pin to a valid logic level
(high or low) to prevent a floating-input buffer. If EXCLK is used, toggling the
EXCLK input pin after the FPGA enters user mode will not effect the enhanced
configuration device operation.
This pin selects a 2-ms or 100-ms POR counter delay during power up. When
PORSEL is low, POR time is 100 ms. When PORSEL is high, POR time is 2 ms.
This pin must be connected to a valid logic level.
For normal operation, this test pin must be connected to GND.
For normal operating, this test pin must be connected to V
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16
CC
CC
if the JTAG circuitry is not used.
if the JTAG circuitry is not used.
CC
Description
Description
on the board even when you are not using the
white paper.
© December 2009 Altera Corporation
CCQ
of the Intel flash die
CC
.
CC
without using any
Pin Description