DP8421ATVX-25 National Semiconductor, DP8421ATVX-25 Datasheet - Page 38

• Manufacturer Part Number: DP8421ATVX-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421ATVX-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421ATVX-25

10 0 Dual Accessing (DP8422A)
10 2 PORT B WAIT STATE SUPPORT
Advanced transfer acknowledge for Port B ATACKB is
used for wait state support for Port B This output will be
asserted when RAS for the Port B access is asserted as
shown in Figures 33a and 33b Once asserted this output
will stay asserted until AREQB is negated With external
logic ATACKB can be made to interface to any CPU’s wait
input as shown in Figure 33c
10 3 COMMON PORT A AND PORT B DUAL PORT
FUNCTIONS
An input LOCK and an output GRANTB add additional
functionality to the dual port arbitration logic LOCK allows
A Extend ATACK to
C Synchronize ATACKB to CPU B Clock This is useful if CPU B runs asynchronous to the DP8422
T (
Clock) after RAS goes low
FIGURE 33c Modifying Wait Logic for Port B
FIGURE 33a Non-Delayed Port B Access
FIGURE 33b Delayed Port B Access
TL F 8588– 30
(Continued)
38
Port A or Port B to lock out the other port from the DRAM
When a Port is locked out of the DRAM wait states will be
inserted into its access cycle until it is allowed to access
memory GRANTB is used to multiplex the input control sig-
nals and addresses to the DP8422A
10 3 1 GRANTB Output
The output GRANTB determines which port has current ac-
cess to the DRAM array GRANTB asserted signifies Port B
has access GRANTB negated signifies Port A has access
to the DRAM array
B Extend ATACK to 1T after RAS goes low
TL F 8588– 32
TL F 8588 – E6
TL F 8588 – E7
TL F 8588– 31