LTC1646CGN Linear Technology, LTC1646CGN Datasheet - Page 6

• Manufacturer Part Number: LTC1646CGN
• Description: IC CNTRLR HOTSWAP PCIDUAL 16SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC1646CGN

• Applications: CompactPCI™
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1646
RESETOUT (Pin 1): Open Drain Digital Output. Connect
the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of RESETIN and
PWRGD (see Table 4).
TIMER (Pin 2): Current Fault Inhibit Timing Input. Connect
a capacitor from TIMER to GND. With the chip turned off,
the TIMER pin is internally held at GND. When the chip is
turned on, a 5µA pull-up current source is connected to
TIMER. Current limit and voltage compliance faults will be
ignored until the voltage at the TIMER pin is greater than
1.25V.
FAULT (Pin 3): Open Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Faults are ignored
while the voltage at the TIMER pin is less than 1.25V. Once
the TIMER cycle is complete, FAULT will pull low and the
chip will latch off in the event of an overcurrent fault. The
chip will remain latched in the off state until the OFF/ON pin
is cycled high then low or the power is cycled.
Forcing the FAULT pin low with an external pull-down will
cause the chip to be latched into the off state after a 21µs
deglitching time.
TYPICAL PERFOR A CE CHARACTERISTICS
PI FU CTIO S
6
U
U
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
RESETOUT, PWRGD and FAULT
Output Low Voltage vs I
U
1
W
I
2
SINK
(mA)
U
3
SINK
4
90°C
25°C
–45°C
1646 G22
5
PWRGD (Pin 4) :Open Drain Power Good Digital Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V
4.65V. When either of the supplies falls below its power
good threshold voltage, PWRGD will go high after a 50µs
deglitching time.
5V
pull low until the 5V
input supply is available, tie the 5V
in order to disable the 5V
GND (Pin 6): Chip Ground
3V
pull low until the 3V
3.3V input supply is available, tie the 3V
5V
3V
lockout circuit prevents the switches from turning on
when the voltage at the 3V
input supply is available, connect a diode between 5V
and 3V
Figure 11.
OUT
OUT
OUT
IN
(Pin 8): 3.3V Supply Sense Input. An undervoltage
(Pin 7): 3.3V Output Sense. The PWRGD pin will not
(Pin 5): 5V Output Sense. The PWRGD pin will not
pin.
IN
180
160
140
120
100
80
60
40
20
0
(tie anode to 5V
–50
5V
Impedance vs Temperature
OUT
–25
/3V
OUT
OUT
TEMPERATURE (°C)
OUT
0
pin voltage exceeds 4.65V. If no 5V
Discharge
pin voltage exceeds 2.90V. If no
IN
OUT
25
IN
pin is less than 2.5V. If no 3.3V
and cathode to 3V
3VOUT
power good function.
50
OUT
75
≥ 2.9V and V
pin to the 3V
1646 G23
100
OUT
pin to the
IN
5VOUT
OUT
). See
1646fa
pin
IN
≥