IR22141SSTRPBF International Rectifier, IR22141SSTRPBF Datasheet - Page 11

• Manufacturer Part Number: IR22141SSTRPBF
• Description: IC DVR HALF BRIDGE IC 24SSOP
• Manufacturer: International Rectifier

Specifications of IR22141SSTRPBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 1200V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Family Hvic: General Purpose HVICs
• Channels: 2
• Topology: Half Bridge
• Application: General Purpose / Motor Control
• Voffset: 1200
• Io+ (ma): 2000
• Io- (ma): 3000
• Separate Power And Logic Ground: Yes
• Uvlo: Vcc / Vbs
• Vbsuv+ / Vccuv+ Min (v): 9.3
• Vbsuv+ / Vccuv+ Typ (v): 10.2
• Vbsuv+ / Vccuv+ Max (v): 11.4
• Vbsuv- / Vccuv- Min (v): 8.7
• Vbsuv- / Vccuv- Typ (v): 9.3
• Vbsuv- / Vccuv- Max (v): 10.3
• Dt / Sdt Min (ns): 5700
• Dt / Sdt Typ (ns): 9250
• Dt / Sdt Max (ns): 13500
• T On Min (ns): 220
• T On Typ (ns): 440
• T On Max (ns): 660
• T Off Min (ns): 220
• T Off Typ (ns): 440
• T Off Max (ns): 660
• Fault Reporting: Yes
• Package: 24 Lead
• Part Status: Active & Preferred
• Special Features: Soft Shutdown and Desaturation Detection
• For Use With: IRMD2214SS - KIT DESIGN EVAL BOARD IR2214SSIRMD22141SS - KIT DESIGN EVAL BOARD/IR22141SS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Undervoltage
Fault Cleared
Fault Clear
Anti Shoot
Operation
Shutdown
Operation
Shutdown
Shutdown
(finishing)
(entering)
Through
Normal
Freeze
Soft
Soft
††
†
SY_FLT automatically resets after the SSD event is over, without requiring FLT_CLR to be asserted. To
avoid FLT_CLR conflicting with the SSD sequence of operations, in the event of a SSD during normal
operation it is recommended not to apply FLT_CLR while SY_FLT is active. At power supply start-up
instead, it is recommended to keep FLT_CLR active to prevent spurious diagnostic signals being
generated, as described in section 1.1 Start-Up Sequence and in section 1.4.5 Fault Management at
Start-up.
Holding FLT_CLR high all time will not allow the gate driver to latch the FAULT status and migth
compromise power system protection.
Hin
H
H
X
X
X
X
X
X
1
0
0
1
1
0
IN
IN
Lin
L
L
L
INPUTS
X
X
X
X
X
0
1
0
1
0
1
IN
IN
IN
HO/LO Status
LO
LO/HO
n-1
SSD
FLT_CLR
0
1
/HO
Logic Table: Output Drivers Status Description
X
X
X
X
1
0
0
0
0
0
0
0
0
n-1
Output follows inputs (in=1->out=1, in=0->out=0)
HOP/LOP
SSD: desat (out)
HOLD: freezing
HiZ
HiZ
0 (HOLD)
SY_FLT
1
______
(in)
X
X
X
1
1
1
1
1
1
†
Output keeps previous status
(SSD)
(SSD)
(SSD)
(SSD)
INPUT/OUTPUT
11
HON/LON
HiZ
HiZ
0
FAULT: diagnostic
SD: shutdown (in)
_________
FAULT/SD
0 (FAULT)
0 (SD)
(out)
1
(FAULT)
(FAULT)
(FAULT)
1
1
1
1
1
1
1
1
††
SSDH/SSDL
IR21141/IR22141SSPbF
HiZ
HiZ
0
Undervoltage
X: don’t care
V
Yes
Yes: V< UV
No : V> UV
No
No
No
No
No
No
No
No
No
No
No
No
X
threshold
threshold
CC
© 2009 International Rectifier
Yes
V
No
No
No
No
No
No
No
No
No
No
No
X
X
BS
HO
SSD
HO
HO
HO
OUTPUTS
0
1
0
0
0
0
0
0
0
0
n-1
LO
SSD
LO
LO
LO
LO
0
0
1
0
0
0
0
0
0
n-1