IR3500AMTRPBF International Rectifier, IR3500AMTRPBF Datasheet
IR3500AMTRPBF
Specifications of IR3500AMTRPBF
Related parts for IR3500AMTRPBF
IR3500AMTRPBF Summary of contents
Page 1
DESCRIPTION The IR3500A Control IC combined with an xPHASE3 to implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a ...
Page 2
ORDERING INFORMATION Device IR3500A MTRPBF * IR3500A MPBF *Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any ...
Page 3
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ V ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 CCL ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the ...
Page 4
PARAMETER Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time V(IIN) – V(OCSET) = 500 mV SS/DEL to FB Input Offset With FB = 0V, adjust ...
Page 5
PARAMETER Open Voltage Loop Detection Measure V(VCCL) - V(EAOUT), Threshold Relative to Error Amplifier maximum voltage. Open Voltage Loop Detection Measure PHSOUT pulse numbers from Delay V(EAOUT) = V(VCCL) to PGOOD = low. Enable Input VR 11 Threshold Voltage ENABLE ...
Page 6
PARAMETER VDRP Buffer Amplifier Input Offset Voltage Source Current Sink Current Unity Gain Bandwidth Slew Rate IIN Bias Current PGOOD Output Output Voltage Leakage Current Under Voltage Threshold-VO decreasing Under Voltage Threshold-VO increasing Under Voltage Threshold Hysteresis VCCL_DRV Activation Threshold ...
Page 7
SYSTEM SET POINT TEST IR3500 VDAC BUFFER AMPLIFIER + ISOURCE FAST VDAC ISINK - IVDAC CURRENT SOURCE IROSC GENERATOR Figure 2 - System Set Point Test Circuit for VR11 VID IR3500 VDAC BUFFER AMPLIFIER + FAST ISOURCE VDAC ISINK - ...
Page 8
PIN DESCRIPTION PIN# PIN SYMBOL 1-8 VID7-0 Inputs to VID Converter. 9 ENABLE Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin as the logic state ...
Page 9
SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the XPhase3 with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage ...
Page 10
IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback ...
Page 11
The error amplifier is a high speed amplifier with 110 dB of open loop gain not unity gain stable. PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE DUTY CYCLE INCREASE OPERATION DUE TO LOAD INCREASE ...
Page 12
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (R voltage across Ccs is proportional ...
Page 13
Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If ...
Page 14
A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series ...
Page 15
ENABLE VBIAS VCCL COMPARATOR ENABLE 250nS - BLANKING INTEL + DELAY 850mV 1.2V AMD COMPARATOR 800mV 1.14V + VCCLDRV - 80mV VCCL REGULATOR 120mV AMPLIFIER DISCHARGE VCCLFB + 4.0V COMPARATOR - 0.94 1.19V VCCL OUTPUT 0.86 0.2V COMPARATOR + VCCL ...
Page 16
TABLE 1 - VIDSEL FUNCTIONALITY VIDSEL VID Table Connection LGND (<0.5V) AMD 5-BIT OPTERON 6. GND AMD 6-BIT (0.7V to 83% of FLOAT) FLOAT (typ. VR11 8-BIT 83% of VR11w/wo boot Threshold) VCCL (4.5V-7V) VR11 8-BIT TABLE 2 ...
Page 17
TABLE 3 - VR11 VID TABLE (PART1) Hex (VID7:VID0) Dec (VID7:VID0) 00 00000000 01 00000001 02 00000010 03 00000011 04 00000100 05 00000101 06 00000110 07 00000111 08 00001000 09 00001001 0A 00001010 0B 00001011 0C 00001100 0D 00001101 0E ...
Page 18
TABLE 3 - VR11 VID TABLE (PART 2) Hex (VID7:VID0) Dec (VID7:VID0) 80 10000000 81 10000001 82 10000010 83 10000011 84 10000100 85 10000101 86 10000110 87 10000111 88 10001000 89 10001001 8A 10001010 8B 10001011 8C 10001100 8D 10001101 ...
Page 19
TABLE 4 - AMD 5-BIT TABLE FOR OPTERON VID4 Note: VID_SEL tied to LGND. V(VDAC) is pre-positioned 50mV higher than VID values listed above for load line positioning. VID is measured at EAOUT with EAOUT shorted to FB, ROSC=50 K ...
Page 20
IVSETPT Remote Sense Amplifier Figure 10 - Temperature compensation of inductor DCR Remote Voltage Sensing VOSEN+ and VOSEN- are used for remote sensing and connected directly to the load. The remote sense differential amplifier with high speed, low input offset ...
Page 21
Figure 11 depicts start-up sequence of converter with VR 11 VID with boot voltage, which is selected by VIDSEL pin based on Table 1. If there is no fault, the SS/DEL pin will start charging when the enable crosses the ...
Page 22
VCC (12V) ENABLE VID VDAC 4.0V 3.92V 1.4V SS/DEL EAOUT VOUT VRRDY START DELAY (TD1) Figure 12 - Start-up sequence of converter without boot voltage Constant Over-Current Control during Soft Start The over current limit threshold is set by a ...
Page 23
ENABLE INTERNAL OC DELAY 4.0V 3.92V 3.88V SS/DEL 1.1V EA VOUT VRRDY OCP THRESHOLD IOUT START-UP WITH OUTPUT SHORTED Figure 13 - Over Current Protection waveforms during and after soft start Linear Regulator Output (VCCL) The IR3500A has a built-in ...
Page 24
VCCL Under Voltage Lockout (UVLO) The IR3500A has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage instead, which is used for the gate drivers of phase ICs and circuits in control IC and phase ...
Page 25
At the same time IIN pin (ISHARE of phase ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure ...
Page 26
VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ROSC/OVP 1.6V Figure 16 - Over-voltage protection during power-up 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 17 - Over-voltage protection with ...
Page 27
VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT 1.73V VOLTAGE (VOSEN+) VID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V <Vo < 1.73V During dynamic VID ...
Page 28
VID (FAST VDAC) VDAC OV THRESHOLD OUTPUT VOLTAGE VDAC (VO) NORMAL OPERATION Figure 19 - Over-voltage protection during dynamic VID Open Daisy Chain Protection IR3500A checks the daisy chain every time it powers up. It starts a daisy chain pulse ...
Page 29
APPLICATIONS INFORMATION Q1 12V RVCCLDRV RVCCLFB1 RVCCLFB2 CVCCL 4.7uF VR READY VIDSEL VID7 1 24 VID7 LGND ROSC VID6 2 23 VID6 ROSC / OVP CSS/DEL VID5 3 22 VID5 SS/DEL IR3500 RVDAC 4 21 VID4 VID4 VDAC CONTROL ROCSET ...
Page 30
Q1 12V ROVP1 RVCCLDRV RVCCLFB1 RVCCLFB2 CVCCL 4.7uF Q2 VR READY VIDSEL VID7 1 24 VID7 LGND ROSC VID6 2 23 VID6 ROSC / OVP CSS/DEL VID5 3 22 VID5 SS/DEL IR3500 RVDAC VID4 4 21 VID4 VDAC CONTROL ROCSET ...
Page 31
DESIGN PROCEDURE Oscillator Resistor Rosc The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of each phase converter equals the PHSOUT frequency, which is set by the external resistor R curve in Figure 23. ...
Page 32
The soft start delay time (TD1) and VR ready delay time (TD3) are determined by (8) to (9) respectively Once C is chosen, the minimum over-current fault ...
Page 33
No Load Output Voltage Setting Resistor R A resistor between VSETPT pin and VDAC is used to create output voltage offset V difference between V voltage and output voltage at no load condition. R DAC I is the current flowing ...
Page 34
R R TMAX THERM Select the series resistor R HOTSET2 operational temperature range. Then calculate R TMAX from (23 HOTSET 1 VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to ...
Page 35
∗ ∗ optional and may be needed in some applications to ...
Page 36
π ∗ ∗ π ∗ ∗ π ∗ ∗ ...
Page 37
The soft start delay time is − DEL = = = TD 1 − CHG The ...
Page 38
No Load Output Voltage Setting Resistor R From Figure 24, the bias current of VSETPT pin is 11.9uA with R − TOFST = = R VSETPT VSETPT VCCL ...
Page 39
2000 MAX DRP ∗ π ∗ ∗ ∗ ∗ ∗ ...
Page 40
The soft start time is − DEL − CHG The VID ...
Page 41
Calculate constant K the ratio of inductor peak current over average current in each phase, P, ⋅ ⋅ − ⋅ ⋅ − ⋅ − ...
Page 42
VCCL TMAX HOTSET HOTSET VOLTAGE LOOP COMPENSATION Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and phase margin ...
Page 43
Figure 23 - Frequency variation with ROSC. Figure 24 - ISETPT, OCSET with ROSC. Page IR3500A July 28, 2009 ...
Page 44
LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. • ...
Page 45
PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
Page 46
SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
Page 47
STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
Page 48
PACKAGE INFORMATION 32L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ JA Data and specifications subject ...