LTC3588EDD-2#TRPBF Linear Technology, LTC3588EDD-2#TRPBF Datasheet - Page 8

• Manufacturer Part Number: LTC3588EDD-2#TRPBF
• Description: IC ENERGY HARVESTING PSU 10DFN
• Manufacturer: Linear Technology

Specifications of LTC3588EDD-2#TRPBF

• Applications: Energy Harvesting
• Current - Supply: 950nA
• Voltage - Supply: 2.7 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC3588-2
OPERATION
The LTC3588-2 is an ultralow quiescent current power
supply designed specifi cally for energy harvesting and/or
low current step-down applications. The part is designed to
interface directly to a piezoelectric or alternative A/C power
source, rectify a voltage waveform and store harvested
energy on an external capacitor, bleed off any excess power
via an internal shunt regulator, and maintain a regulated
output voltage by means of a nanopower high effi ciency
synchronous buck regulator.
Internal Bridge Rectifi er
The LTC3588-2 has an internal full-wave bridge rectifi er
accessible via the differential PZ1 and PZ2 inputs that
rectifi es AC inputs such as those from a piezoelectric
element. The rectifi ed output is stored on a capacitor at
the V
buck converter. The low-loss bridge rectifi er has a total
drop of about 400mV with typical piezo generated currents
(~10μA). The bridge is capable of carrying up to 50mA.
One side of the bridge can be operated as a single-ended
DC input. PZ1 and PZ2 should never be shorted together
when the bridge is in use.
Undervoltage Lockout (UVLO)
When the voltage on V
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output capacitor.
A wide (~2V) UVLO hysteresis window allows a portion of
the energy stored on the input capacitor to be transferred
to the output capacitor by the buck. When the input capaci-
tor voltage is depleted below the UVLO falling threshold
the buck converter is disabled. Extremely low quiescent
current (830nA typical, V
to accumulate on the input capacitor in situations where
energy must be harvested from low power sources.
Internal Rail Generation
Two internal rails, CAP and V
are used to drive the high side PMOS and low side NMOS
of the buck converter, respectively. Additionally the V
rail serves as logic high for output voltage select bits D0
and D1. The V
the CAP rail is regulated at 4.8V below V
intended to be used as external rails. Bypass capacitors
8
IN
pin and can be used as an energy reservoir for the
IN2
rail is regulated at 4.8V above GND while
IN
IN
rises above the UVLO rising
= 12V) in UVLO allows energy
IN2
, are generated from V
IN
. These are not
IN
and
IN2
are connected to the CAP and V
reservoirs for driving the buck switches. When V
4.8V, V
shows the ideal V
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V
capacitor through an inductor to a value slightly higher
than the regulation point. It does this by ramping the
inductor current up to 260mA through an internal PMOS
switch and then ramping it down to 0mA through an
internal NMOS switch. This effi ciently delivers energy
to the output capacitor. The ramp rate is determined by
V
falls below the UVLO falling threshold before the output
voltage reaches regulation, the buck converter will shut
off and will not be turned on until the input voltage again
rises above the UVLO rising threshold. During this time
the output voltage will be loaded by approximately 100nA.
When the buck brings the output voltage into regulation
the converter enters a low quiescent current sleep state
that monitors the output voltage with a sleep comparator.
During this operating mode load current is provided by
the buck output capacitor. When the output voltage falls
below the regulation point the buck regulator wakes up
and the cycle repeats. This hysteretic method of providing
a regulated output reduces losses associated with FET
switching and maintains an output at light loads. The buck
delivers a minimum of 100mA of average current to the
output when it is switching.
OUT
IN
, V
sense pin. The buck converter charges an output
OUT
IN2
Figure 1. Ideal V
, and the inductor value. If the input voltage
is equal to V
18
16
14
12
10
8
6
4
2
0
0
IN
, V
IN
IN2
IN
5
, V
and CAP is held at GND. Figure 1
and CAP relationship.
IN2
V
IN
CAP
(V)
and CAP Relationship
V
IN2
IN
10
pins to serve as energy
V
IN2
35882 F01
15
IN
is below
35882f