LM81BIMT-3/NOPB National Semiconductor, LM81BIMT-3/NOPB Datasheet - Page 26

• Manufacturer Part Number: LM81BIMT-3/NOPB
• Description: IC MONITOR SYS HARDWARE 24TSSOP
• Manufacturer: National Semiconductor

Specifications of LM81BIMT-3/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.8 V ~ 3.8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Monitored Voltage: 2.5 V , 3.3 V , 5 V , 12 V
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No
• Supply Voltage (max): 3.8 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 400 uA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM81BIMT-3; *LM81BIMT-3/NOPB; LM81BIMT-3

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Bit
0
1
2
3
4
5
6
7
Functional Description
13.3 Configuration Register — Address 40h
Power on default –
Start
INT Enable
Reserved
INT_Clear
RESET
Reserved
CI_Clear
INITIALIZATION
Name
<
7:0
>
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
= 00001000 binary
Read/
Write
(Continued)
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT_Clear” bit.
At start up, limit checking functions and scanning begin. Note, all limits should be set
in the Value RAM before setting this bit HIGH.
A one enables the INT Interrupt output.
A one disables the INT output without affecting the contents of Interrupt Status
Registers. The device will stop monitoring. It will resume upon clearing of this bit.
A one outputs at least a 20 ms active low reset signal at RESET. This bit is cleared
once the pulse has gone inactive.
A one outputs a minimum 20 ms active low pulse on the CI pin. The register bit self
clears after the pulse has been output. This bit is mirrored in the CI Clear Register bit
7.
A one restores power on default value to the Configuration Register, Interrupt Status
Registers, Interrupt Mask Registers, CI Clear Register, VID/Fan Divisor Register,
VID4, Temperature Configuration Register, and the Extended Mode Registers. This bit
clears itself since the power on default is zero.
26
Description