NCP1381DR2G ON Semiconductor, NCP1381DR2G Datasheet
NCP1381DR2G
Specifications of NCP1381DR2G
NCP1381DR2GOSTR
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NCP1381DR2G Summary of contents
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... Timer 5 Skip/OVP ORDERING INFORMATION Device Package NCP1381DR2G SOIC--14 (Pb--Free) NCP1382DR2G SOIC--14 (Pb--Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: MARKING ...
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HV PFC Stage + To PFC’ OVP GTS_ADJ BO DMG Skip GTS_ADJ PIN FUNCTION DESCRIPTION Pin# Symbol 1 GTS_ADJ GTS Level Adjustment 2 BO Brown--out 3 DMG Detects the Zero Voltage Crossing Point 4 Timer Fault Timer 5 ...
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INTERNAL CIRCUIT ARCHITECTURE ADJ_GTS ADJ_GTS Section + 250 BOComp. 240 mV/ 500 CLK DMG R Timeout Delayed V latchDem -- + + DMG 3 ...
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MAXIMUM RATINGS TABLE Symbol V Maximum Power Supply Voltage on Pin 10 (V supply Maximum Current in Pin 10 (V Maximum Current in Pin 11 (GTS) Maximum Current in Pin 9 (DRV) Power Supply Voltage on all Other Pins Except ...
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ELECTRICAL CHARACTERISTICS (For typical values T = 25C, for min/max values T J Symbol GO- -TO- -STANDBY R Pin 11 Output Impedance (or R GTS is Closed) R Skip Adjustment Output Impedance skip V Default Skip Cycle Level skip Hyst_ratio ...
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... Due to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. This is further strengthened by ON Semiconductor’s Soft- -Skip technique, which forces the peak current in skip to gradually increase. In case the default skip value would be too large, connecting a resistor to the Pin 6 will reduce or increase the skip cycle level ...
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Startup sequence When the power supply is first connected to the mains outlet, the NCP1381/82 starts to consume current. However, due to a novel architecture, the internal startup current is kept very low, below maximum value. ...
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Figure 5. A Typical Startup Sequence Followed by a Faulty Condition Startup Resistor Calculation For the sake of the example, we will go through the calculation of the startup element. Suppose that we have the following information: VCC = 15 ...
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V CC DRV 100 ms < 100 ms Bunch Length Given by Timer Bunch Length Given by VCC If V drops below VCC during a portion where the timer CC OFF counts, pulses are immediately stopped and the latchoff phase ...
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OFF As one can see from Figure 7, a parasitic ringing takes place at the switch opening: this is the leakage inductance contribution. Unfortunately, this leakage can be detected as a core reset event if no precaution is taken. ...
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CLK R Demag 7.00 5.00 Possible Restart 3.00 1. --1.00 Figure 10. Core Reset Detection is Done Through the Monitoring of a Dedicated Auxiliary Winding ...
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Figure 12 depicts the internal comparator arrangement. The FB pin level is permanently compared to a fixed level also available on Pin 5 for adjustment result, the skip user can wire a resistor to ground and ...
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Figure 13. The Soft- -start Starts During Skip Mode and Smooths the Current Signature Demag Restart Current Sense and Timeout Restart 8 ms Figure 14. The 8 ms Timeout Helps to Restart the Controller Figure 15. The Internal Soft- -start ...
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Required I 2.9 2.8 2.7 2.6 2.5 200 250 300 V , VOLTAGE (V) in Figure 16. Peak Current Evolution with Input Voltage Converter at Constant Output Power (100 result, we ...
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As one can observe, the output power runs out of the initial 100 W specification when we enter the high line region. To cope with this problem, we need to compensate the controller in such a way that its peak ...
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Demag To Demag Comp latchdem Figure 22. Plateau Sensing Overvoltage Protection External Latchoff By lifting up Pin 5 above V (3.5 V Typ - - NCP1381, latch 2.5 V Typ - - NCP1382), the circuit is ...
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Unfortunately, the situation complicates with QR converters since the input voltage plays a significant role in the feedback voltage evolution. A case can happen where the converter is supplied by ...
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Ext, SIgnal (FB, AUX) ADJ_GTS + R hyst -- + 250 mV Figure 27. The SW Switch is Turned Off After the Timer Confirms the Presence of a Standby During the startup sequence, the PFC is ...
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During the startup sequence, the converter starts by itself, the PFC is in off mode (SW switch is open). However, when the I Flag is down, without delay, the PFC is turned on short- -circuit mode, the I ...
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V × V (line) (timing) B1 Voltage Δ Bulk Line Timing R upper + + lower V1 Timing 0 PWL 0 0 10s 0.2 V2 Line 0 SIN 150 50 Figure 30. ...
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V bulk Activated During Fault Only + -- + VCC R ON startup VCC latch + CC3 + VCC ON VCC OFF 8 Fault S&R are Positive R Edge Triggered Figure ...
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Plot1 160 120 Plot2 25 15 5.0 --5.0 6.5 Plot3 4.5 2.5 500m --1.5 10.0m 30.0m The mains goes up and down, the bottom signal stops pulses at low mains but reactivates them when V 35.0 ...
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Plot2 25 15 5.0 --5.0 41.3m 6.5 Plot3 4.5 2.5 500m --1.5 41.3m 14 Plot1 10 6.0 2.0 --2.0 41.3m The B comes back in the upslope but the logic 2 waits until UVOL circuitry detects ...
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BO Interruption 50.0m A mix of conditions, BO, short--circuit and UVLO fault are represented on this diagram. In BO, the pulses (pulse ok signal) are started and there is no latch--off phase. In short--circuit, pulses ...
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... M 14X 0.58 *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Soft--Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...