NCP1381 ONSEMI [ON Semiconductor], NCP1381 Datasheet
NCP1381
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NCP1381 Summary of contents
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... NCP1381 Low−Standby High Performance PWM Controller Housed in a SO−14 package, the NCP1381 includes everything needed to build rugged and efficient Quasi−Resonant (QR) Switching Power Supplies. When powered by a front−end Power Factor Correction circuitry, the NCP1381 automatically disconnects the PFC controller in low output loading conditions (with an adjustable level), thus improving the standby power ...
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... This pin cumulates two different functions: the standard sense function plus an adjustable offset voltage providing the adequate level of Overpower Protection. − With a drive capability of $500 mA/800 mA, the NCP1381 can drive large Q MOSFETs. The controller accepts voltages and features an UVLO typical. ...
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... ON Fault / 4 SS Timer 4 I PFlag LEB Skip/ 5 OVP OPP Offset Latchoff latch Figure 2. Internal Circuit Architecture NCP1381 Timer Management CC UVLO, Latchoff + − Timer P Flag 4 ms DRV Shot to Latch S Q CLK − ...
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... Propagation Delay from CS Detected to Gate Turned off (Pin 9 Loaded DELCS by 1 nF) T Leading Edge Blanking Duration LEB S Typical Internal Soft−start Period at Startup Start NCP1381 Rating ), Pin 9 (DRV), and Pin 11 (GTS Pin 9 (DRV), Pin 3 (DMG) and CC ), Pin 9 (DRV) and Pin 11 (GTS 0° ...
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... Brown−out Level Low low I Brown−out Pin Input Bias Current BO T Temperature Shutdown, Maximum Value SD TSD Hysteresis While in Temperature Shutdown hyst NCP1381 = 0°C to +125° unless otherwise noted Rating between Pin 10 and Pin 11 when SW dson 3 Decreasing pin ...
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... The NCP1381 includes all necessary features to help building a rugged and safe switching power supply featuring an extremely low standby power. The below bullets detail the benefits brought by implementing the NCP1381 controller. • Current−mode operation with Quasi−Resonant Operation: Implementing peak current mode control, the NCP1381 waits until the drain− ...
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... Startup sequence When the power supply is first connected to the mains outlet, the NCP1381 starts to consume current. However, due to a novel architecture, the internal startup current is kept very low, below maximum value. The current delivered by the startup resistor also feeds the V capacitor and its voltage rises ...
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... If we want a startup below 2 s, then the charging current flowing inside the V CC NCP1381 above: I the above 180 mA. 3. The minimum input voltage 1.414 = 120 V. ...
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... Vds(t) has the time to go through a minimum, also called valley. Therefore, when we will finally reactivate the power MOSFET, its drain−to−source voltage will be minimum, reducing capacitive losses but also its gate−charge value, since the Miller effect gets diminished at low Vds. NCP1381 VCC ON VCC OFF t ON Figure 7. Typical Quasi− ...
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... D flip−flop when the 8 ms timer has not been completed, the restart is ignored until a new demagnetization signal comes in. This offers the benefit to clamp the maximum switching NCP1381 frequency 125 kHz. Please note that the 8 ms timer clamps everything is met, then the flip− ...
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... Fault Figure 9. Internal QR Architecture Skipping Cycle Mode The NCP1381 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 6 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current ...
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... To help in this situation, the NCP1381 implements timeout generator: each time the 45 mV crossing occurs, the timeout is reset. So, as long as the ringing becomes too low, the timeout generator starts to count and after 8 ms, it delivers its “ ...
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... Smooths the Current Signature Demag Restart Current Sense and Timeout Restart 8 ms Figure 14. The 8 ms Timeout Helps to Restart the Controller NCP1381 Figure 15. The Internal Soft−start is Activated During Each Skipped Cycles Overpower Compensation A FLYBACK converter operating in Borderline Conduction Mode (BCM) transfers energy from primary to ...
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... V , VOLTAGE (V) in Figure 18. Output Power Evolution with the Input Voltage (No Compensation) NCP1381 4 3 Pmax 350 400 0 Figure 17. I variable offset that will compensate the maximum output power. This would result in a variable I by the dashed line on Figure 16 ...
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... 0.0025 x in Overvoltage Protection The NCP1381 features an overvoltage protection made by sensing the plateau voltage at the switch turn−off. However, a sampling delay is introduced to avoid considering the leakage inductance. When the demagnetization pin goes above V demlatch is maintained when the sampling pulse arrives, then a fault is latched ...
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... The cheapest option is obtained when wiring a simple zener diode in series with the monitored line. Care must be taken to limit the excursion of the skip pin before fully latching the controller. NCP1381 700 500 300 100 ...
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... V This is okay. The drawback of Figure 26 is the higher forced level for lower power outputs. In our example adapter, the NCP1381 BCS Where FB CS setpoint. In our controller, this ratio now ...
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... Figure 27. The SW Switch is Turned Off After the Timer Confirms the Presence of a Standby During the startup sequence, the PFC is disabled (in short−circuits too) and runs as soon as the I detected, the timer runs and confirms the standby mode. When the mode is left, there is no delay and the PFC is turned−on immediately. NCP1381 + − ...
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... Pin 2 to create a brown−out detection. Please note that this technique does not use a current source for the hysteresis but rather a capacitor. It offers a way to freely select the resistive bridge impedance. NCP1381 BOK Figure 29. A Way to Implement a BOK Detector Flag always P The calculation procedure for R a few lines of algebra ...
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... When we reach 15 V, the logic checks whether the BOK gives the green light. If not mA. The logic arrangement is made in such a way that if the mains comes back asynchronously the upslope), we always restart at V Figure 34 and 35 confirm the good restart synchronization with the 15 V level. NCP1381 Bulk + 2 C ...
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... Figure 32 also includes the short−circuit latch−off phase generation. The difference between behaviors short−circuit, is the lack of latch−off phase in brown−out conditions BO, whereas it goes down and short−circuit conditions. Figure 36 shows how V short−circuit is detected conditions, the PFC is disabled as in UVLO conditions. NCP1381 2 + − ...
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... Plot3 4.5 P Reset ON 2.5 500m −1.5 14 Plot1 6.0 2.0 −2.0 41.3m The B comes back in the descent but the logic waits until the UVOL circuitry detects restart the controller. OK NCP1381 Bulk Voltage V CC Internal OK Signal 50.0m 70.0m TIME (s) Figure 33. 41.8m 42.4m 42.9m TIME (s) Figure 34. http://onsemi.com 90. 43.5m ...
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... UVOL circuitry detects restart the Control- OK ler. 8.50 18.0 6.50 14.0 4.50 10.0 2.50 6.00 V 500m 2.00 20.0m In short−circuit, the V drops to VCC CC latch given by the fault timer (purposely reduced on this simulation). Should a VCC be accordingly truncated. NCP1381 V CC 41.8m 42.4m 42.9m P Reset ON 41.8m 42.4m 42. 41.8m 42.4m 42.9m TIME (s) Figure 35 ...
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... V capacitor. The PFC will be shutdown until BO CC comes back and a clean startup sequence has properly ended. Soft−start The NCP1381 features a soft−start activated during the power on sequence (P ) and in short−circuit conditions to ON lower the acoustical noise in the transformer. As soon as ...
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... ORDERING INFORMATION Device NCP1381DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NCP1381 Package SOIC−14 (Pb−Free) http://onsemi.com 25 † Shipping 2500 / Tape & Reel ...
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... C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP1381/D _ ...