ADP3209CJCPZ-RL ON Semiconductor, ADP3209CJCPZ-RL Datasheet - Page 22

• Manufacturer Part Number: ADP3209CJCPZ-RL
• Description: IC CTLR BUCK 5BIT 1PH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The design parameters for a typical IMVP-6+-compliant GPU
core VR application are as follows:
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SETTING THE CLOCK FREQUENCY FOR PWM
In PWM operation, the ADP3209 uses a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(RT). The clock frequency determines the switching frequency,
which relates directly to the switching losses and the sizes of the
inductors and input and output capacitors. For example, a clock
frequency of 300 kHz sets the switching frequency to 300 kHz.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 300 kHz oscillator frequency at a VID voltage of
1.2 V, RT must be 452 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:
where:
7.2 pF and 35 kΩ are internal IC component values.
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
With VARFREQ pulled above 4 V, the ADP3209 operates with a
constant switching frequency. The switching frequency does not
change with VID voltage, input voltage, or load current. In
addition, the DCM operation at light load is disabled, so the
ADP3209 operates in CCM. The value of RT can be calculated
by using the following equation:
is the switching frequency in hertz.
Maximum input voltage (V
Minimum input voltage (V
Output voltage by VID setting (V
Maximum output current (I
Droop resistance (R
Nominal output voltage at 15 A load (V
Static output voltage drop from no load to full load
(∆V) = V
Maximum output current step (∆I
Number of phases (n) = 1
Switching frequency (f
Duty cycle at maximum input voltage (D
Duty cycle at minimum input voltage (D
is the VID voltage in volts.
=
=
2
×
ONL
1
×
6 .
7
− V
+
V
2 .
×
1
7
0 .
pF
OFL
2 .
V
pF
−
O
= 1.25 V − 1.174 V = 76 mV
) = 5.1 mΩ
35
SW
−
kΩ
35
) = 390 kHz
INMIN
INMAX
kΩ
O
) = 15 A
) = 8 V
) = 19 V
VID
O
) = 8 A
) = 1.25 V
OFL
MIN
MAX
) = 1.174 V
) = 0.062 V
) = 0.15 V
Rev. 2 | Page 22 of 32 | www.onsemi.com
(1)
SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION
During the RPM operation, the ADP3209 runs in pseudoconstant
frequency if the load current is high enough for continuous current
mode. While in DCM, the switching frequency is reduced with
the load current in a linear manner. To save power with light
loads, lower switching frequency is usually preferred during
RPM operation. However, the V
IMVP-6+ sets a limitation for the lowest switching frequency.
Therefore, depending on the inductor and output capacitors,
the switching frequency in RPM can be equal to, greater than,
or less than its counterpart in PWM.
A resistor between the VRPM and RPM pins sets the
pseudoconstant frequency as follows:
where:
ramp magnitude (see the Ramp Resistor Selection section for
information about the design of R
If R
switching frequency in RPM operation.
SOFT START AND CURRENT LIMIT
LATCH-OFF DELAY TIMES
The soft start and current limit latch-off delay functions share
the SS pin; consequently, these parameters must be considered
together. First, set C
generated with an 8 µA internal current source. The value for
C
where
IMVP-6+ to be less than 3 ms.
Therefore, assuming a desired soft start time of 2 ms, C
and the closest standard capacitance is 12 nF.
After C
by using the following equation:
where
SS
is the internal ramp capacitor value.
is an external resistor on the RAMP pin to set the internal
is the internal ramp amplifier gain.
R
can be calculated as
= 340 kΩ, the following resistance results in 390 kHz
SS
is the desired soft start time and is recommended in
=
is set, the current limit latch-off time can be calculated
is 7.2 ms.
=
=
8
=
(
. 1
μA
1
2 .
174
4
×
4
V
2
×
×
μA
357
+
×
V
SS
1
+
0 .
for the soft start ramp. This ramp is
1
k
V
0 .
Ω
)
V
×
×
390
0
CCGFX
×
2 .
R
1 (
×
×
kΩ
resistance).
−
1 (
ripple specification of
×
−
×
)
5
. 0
×
pF
062
×
)
390
×
. 1
174
kHz
SS
is 13.3 nF,
=
218
(2)
(3)
(4)
k
Ω