IDT72V51336L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51336L7-5BB8 Datasheet - Page 20

• Manufacturer Part Number: IDT72V51336L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51336L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 36b
• Organization: 2Kx36x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51336L7-5BB8

(REOP). The minimum size for a packet is four words (SOP, two words of data
and EOP). The almost empty flag bus becomes the “Packet Ready” PR flag
bus when the device is configured for packet mode. Valid packets are indicated
when both PR and OV are asserted.
WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)
queue. The device requires two cycles to change queues. Packet mode, has
2 restrictions: <1> An extra word (or filler word) is required to be written after
each packet on the cycle following the queue change to ensure the RSOP in
the old queue is not read out on a queue change because of the first word fall
through. <2> No SOP/EOP is allowed to read/written at cycle (“C” or “I”) the
next cycle after a queue change. For clock frequency (fs) of 133MHz and below
see Application Note AN-398. In this mode, the write port may not obtain 100%
bus utilization.
(see Figure 16, Writing in Packet Mode during a Queue Change). WADEN
goes high signaling a change of queue (clock cycle “B” or “H”). The address
on WRADD at the rising edge of WCLK determines the next queue. Data
presented on Din during that cycle (“B” or “H”) can continue to be written to
the active (old) queue (Q
If WEN is HIGH (inactive) for this clock cycle (H), data will not be written in to
the previous queue (Q
or “I”) will require a filler word to be written to the device. This can be done
by clocking the TEOP twice or by writing a filler word. In packet mode, the multi-
queue is designed under the 2 restrictions listed previously. Note, an
erroneous Packet Ready flag may occur if the EOP or SOP marker shows up
at the next cycle after a queue change. To prevent an erroneous Packet Ready
flag from occurring a filler word should be written into the old queue at the last
clock cycle of writing. It is important to know that no SOP or EOP may be written
into the device during this cycle (“C” or “I”). The write port discrete full flag will
update to show the full status of the newly selected queue (Q
rising edge (“C” or “I”). Data values presented on the data input bus (Din),
can be written into the newly selected queue (Q
on the second cycle (“D” or “J”) following a request for change of queue,
provided WEN is LOW (active) and the new queue is not full. If a selected queue
is full (FF is LOW), then writes to that queue will be prevented. Note, data cannot
be written into a full queue.
Figure 18, Data Input (Transit) packet mode of Operation for timing diagrams.
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
moving to a different queue. The device requires two cycles to change queues.
In Packet Mode, there are 2 restrictions <1> An extra word (or filler word)
should have been inserted into the data stream after each packet to insure the
RSOP in the old queue is not read out on a queue change because of the first
word fall through and this word should be discarded. <2> No EOP/SOP is
allowed to be read/written at cycle (“C” or “I”) the next cycle after a queue
change). For clock frequency of 133Mhz and below see Application Note AN-
398. In this mode, the read port may not obtain 100% bus utilization.
(see Figure 17, Reading in Packet Mode during a Queue Change). RADEN
goes high signaling a change of queue (clock cycle “B” or “I”). The address
on RDADD at the rising edge of RCLK determines the queue. As illustrated
in Figure 17 during cycle (“B”), data can be read from the active (old) queue
(Q
changing queues. REOP for packet located in queue (Q
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
It is required that a full packet be written to a queue before moving to a different
Changing queues requires a minimum of two WCLK cycles on the write port
Refer to Figure 16, Writing in Packet Mode during a Queue Change and
In Packet mode it is required that a full packet is read from a queue before
Changing queues requires a minimum of two RCLK cycles on the read port
A
)), provided both REN and OE are LOW (active) simultaneously with
B
). The cycle following a request for queue change (“C”
A
or Q
B
respectively), provided WEN is LOW (active).
X
) on the rising edge of WCLK
A
) must be read before
B
) at this last cycle’s
20
a queue change request is made (“B”). If REN is HIGH (inactive) for this clock
cycle (“I”), data will not be read from the previous queue (Q
where the multi-queue flow-control device is connected to a shared bus, an
output enable, OE control pin is also provided to allow High-Impedance
selection of the data outputs (Qout). With reference to Figure 17 when changing
queues, a packet marker (SOP or EOP) should not be read on cycle (“C” or
“I”). Reading a SOP or EOP should not occur during the cycles required for
a queue change. It is also recommended that a queue change should not occur
once the reading of the packet has commenced. The EOP marker of the packet
prior to a queue change should be read on or before the queue change. If the
EOP word is read before a queue change, REN can be pulled high to disable
further reads. When the queue change is initiated, the filler word written into
the current queue after the EOP word will fall through followed by and the first
word from the new queue.
well as Figures 12, 14, and 15 for timing diagrams and Table 2, for Read
Address bus arrangement.
the device is configured for packet mode.
PACKET READY FLAG
feature. During a Master Reset the logic “1” (HIGH) on the PKT input signal
(packet mode select), configures the device in packet mode. The PR discrete
flag, provides a packet ready status of the active queue selected on the read
port. A packet ready status is individually maintained on all queues; however
only the queue selected on the read port has its packet ready status indicated
on the PR output flag. A packet is available on the output for reading when both
PR and OV are asserted LOW. If less than a full packet is available, the PR flag
will be HIGH (packet not ready). In packet mode, no words can be read from
a queue until a complete packet has been written into that queue, regardless
of REN.
becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM =
LOW during a master reset), the PRn bus provides packet ready status in 8
queue increments. The PRn bus supports either Polled or Direct modes of
operation. The PRn mode of operation is configured through the Flag Mode
(FM) bit during a Master Reset.
must also be configured for 36 bit write data bus and 36 bit read data bus. The
two most significant bits of the 36-bit data bus are used as “packet markers”.
On the write port these are bits D34 (Transmit Start of Packet,) D35 (Transmit
End of Packet) and on the read port Q34, Q35. All four bits are monitored by
the packet control logic as data is written into and read out from the queues.
The packet ready status for individual queues is then determined by the packet
ready logic.
selected queue as the “Transmit Start of Packet”, TSOP. To further clarify, when
the user requires a word being written to be marked as the start of a packet,
the TSOP input (D34) must be HIGH for the same WCLK rising edge as the
word that is written. The TSOP marker is stored in the queue along with the
data it was written in until the word is read out of the queue via the read port.
being written into the selected queue as the “Transmit End of Packet” TEOP.
When the user requires a word being written to be marked as the end of a
packet, the TEOP input must be HIGH for the same WCLK rising edge as the
word that is written in. The TEOP marker is stored in the queue along with the
data it was written in until the word is read out of the queue via the read port.
Refer to Figure 17, Reading in Packet Mode during a Queue Change as
Note, the almost empty flag bus becomes the “Packet Ready” flag bus when
The multi-queue flow-control device provides the user with a Packet Ready
When packet mode is selected the Programmable Almost Empty bus, PAEn,
When the multi-queue is configured for packet mode operation, the device
On the write port D34 is used to “mark” the first word being written into the
On the write port D35 is used to “mark” the last word of the packet currently
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
B
). In applications