IDT72V51336L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51336L7-5BB8 Datasheet - Page 25

• Manufacturer Part Number: IDT72V51336L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51336L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 36b
• Organization: 2Kx36x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51336L7-5BB8

NOTE:
1. OV Timing
Assertion:
De-assertion:
Read Operation to OV HIGH: t
2. OV Timing when in Packet Mode (36 in to 36 out only)
Assertion:
De-assertion:
Read Operation to OV HIGH: t
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
in36 to out36
(Both ports selected for same queue when the 1
in36 to out36
(Write port only selected for same queue when the D-m Writes
1
in36 to out18
in36 to out9
in18 to out36
in9 to out36
Word is written in until the boundary is reached)
In36 to out36 (Almost Empty Mode)
(Both ports selected for same queue
when the 1
In36 to out36 (Packet Mode)
(Both ports selected for same queue
when the 1
In36 to out18
(Both ports selected for same queue
when the 1
In36 to out9
(Both ports selected for same queue
when the 1
In18 to out36
(Both ports selected for same queue
when the 1
In9 to out36
(Both ports selected for same queue
when the 1
st
Write to OV LOW: t
If t
Write to OV LOW: t
If t
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
SKEW1
SKEW4
I/O Set-Up
is violated there may be 1 added clock: t
is violated there may be 1 added clock: t
st
st
st
st
st
st
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
I/O Set-Up
SKEW1
SKEW4
Output Valid, OV Flag Boundary
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
+ RCLK + t
+ RCLK + t
ROV
ROV
ROV
ROV
OV Goes LOW after 1
(see note 1 below for timing)
OV Goes LOW after 1
(see note 2 below for timing)
OV Goes LOW after 1
(see note 1 below for timing)
OV Goes LOW after 1
(see note 1 below for timing)
OV Goes LOW after 1
(see note 1 below for timing)
OV Goes LOW after 1
(see note 1 below for timing)
st
OV Boundary Condition
SKEW1
SKEW4
PAF/PAFn Goes LOW after
D+1-m Writes
(see note below for timing)
PAF/PAFn Goes LOW after
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
PAF/PAFn Goes LOW after
(see note below for timing)
PAF/PAFn Goes LOW after
(see note below for timing)
([D+1-m] x 2) Writes
([D+1-m] x 4) Writes
PAF & PAFn Boundary
+ 2 RCLK + t
+ 2 RCLK + t
st
st
st
st
st
st
Write
Write
Write
Write
Write
Write
ROV
ROV
25
NOTE:
D = Queue Depth
FF Timing
Assertion:
De-assertion:
NOTE:
D = Queue Depth
m = Almost Full Offset value.
PAF Timing
Assertion:
De-assertion: Read to PAF HIGH: t
PAFn Timing
Assertion:
De-assertion: Read to PAFn HIGH: t
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
In36 to out36
(Both ports selected for same queue
when the 1
In36 to out36
(Write port only selected for queue
when the 1
In36 to out18
(Both ports selected for same queue
when the 1
In36 to out18
(Write port only selected for queue
when the 1
In36 to out9
(Both ports selected for same queue
when the 1
In36 to out9
(Write port only selected for queue
In18 to out36
(Both ports selected for same queue
when the 1
In18 to out36
(Write port only selected for queue
when the 1
In9 to out36
(Both ports selected for same queue
when the 1
In9 to out36
(Write port only selected for queue
when the 1
when the 1
Write Operation to FF LOW: t
Read to FF HIGH: t
If t
SKEW1
Default values:
I/O Set-Up
is violated there may be 1 added clock: t
st
st
st
st
st
st
st
st
st
st
Write Operation to PAF LOW: 2 WCLK + t
If t
Write Operation to PAFn LOW: 2 WCLK* + t
If t
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
SKEW2
SKEW3
SKEW1
is violated there may be 1 added clock: t
is violated there may be 1 added clock: t
if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
+ t
Full Flag, FF Boundary
WFF
WFF
SKEW2
SKEW3
COMMERCIAL AND INDUSTRIAL
+ WCLK + t
FF Goes LOW after D+1 Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after ([D+1] x 2) Writes
(see note below for timing)
FF Goes LOW after (D x 2) Writes
(see note below for timing)
FF Goes LOW after ([D+1] x 4) Writes
(see note below for timing)
FF Goes LOW after (D x 4) Writes
(see note below for timing)
+ WCLK* + t
TEMPERATURE RANGES
FF Boundary Condition
SKEW1
WAF
WAF
PAF
PAF
+WCLK +t
SKEW3
SKEW2
+ 2 WCLK* + t
+ 2 WCLK + t
WFF
WAF
PAF