LMZ12002TZ-ADJ/NOPB National Semiconductor, LMZ12002TZ-ADJ/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMZ12002TZ-ADJ/NOPB
• Description: IC BUCK SYNC ADJ 2A TO-PMOD-7
• Manufacturer: National Semiconductor
• Series: SIMPLE SWITCHER®r
• Type: Point of Load (POL) Non-Isolated with UVLOr

Specifications of LMZ12002TZ-ADJ/NOPB

• Output: 0.8 ~ 6 V
• Number Of Outputs: 1
• Power (watts): 12W
• Mounting Type: Surface Mount
• Voltage - Input: 4.5 ~ 20V
• Package / Case: TO-PMOD-7, Power Module
• 1st Output: 0.8 ~ 6 VDC @ 2A
• Size / Dimension: 0.40" L x 0.54" W x 0.18" H (10.16mm x 13.77mm x 4.57mm)
• Power (watts) - Rated: 12W
• Operating Temperature: -40°C ~ 125°C
• Efficiency: 92%
• Approvals: EN
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 7
• Mounting: Surface Mount
• Case Length: 10.16mm
• Case Height: 4.57mm
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -
• Lead Free Status / Rohs Status: Compliant
• Other names: LMZ12002TZ-ADJTR

The approximate formula for determining the DCM/CCM
boundary is as follows:
I
Following is a typical waveform showing the boundary condi-
tion.
The inductor internal to the module is 10 μH. This value was
chosen as a good balance between low and high input voltage
applications. The main parameter affected by the inductor is
the amplitude of the inductor ripple current (I
calculated with:
I
Where V
mined from equation 10.
If the output current I
I
aware that the lower peak of I
eration is required.
POWER DISSIPATION AND BOARD THERMAL
REQUIREMENTS
For the design case of V
(MAX)
thermal resistance from case to ambient of:
θ
Given the typical thermal resistance from junction to case to
be 1.9 °C/W .Use the 85°C power dissipation curves in the
Typical Performance Characteristics section to estimate the
DCB
LR P-P
L
CA
, the higher and lower peak of I
< (T
≊
= 85°C , and T
V
=V
V
O
J-MAX
IN
V
*(V
O
IN
IN
= 12V, V
*(V
IN
is the maximum input voltage and f
= 12V, V
CCM and DCM Operating Modes
–V
IN
— T
- V
Transition Mode Operation
O
)/(2*10 μH*f
AMB(MAX)
O
O
)/(10µH*f
JUNCTION
O
= 3.3V, I
O
= 3.3V, I
is determined by assuming that I
IN
) / P
= 12V, V
SW
= 125°C, the device must see a
O
SW(CCM)
LR
IC-LOSS
*V
O
= 2A/0.26A 2 μsec/div
must be positive if CCM op-
= 0.29A 2 μsec/div
IN
LR
) (17)
*V
O
can be determined. Be
- θ
= 3.3V, I
IN
JC
) (16)
(18)
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30114714
LR
O
). I
SW
= 2A, T
LR
is deter-
can be
AMB
O
=
13
P
it is 1.2W
θ
To reach θ
effectively. With no airflow and no external heat, a good esti-
mate of the required board area covered by 1 oz. copper on
both the top and bottom metal layers is:
Board Area_cm
As a result, approximately 15.9 square cm of 1 oz copper on
top and bottom layers is required for the PCB design. The
PCB copper heat sink must be connected to the exposed pad.
Approximately thirty six, 10 mils (254 μm) thermal vias spaced
59 mils (1.5 mm) apart must connect the top copper to the
bottom copper. For an example of a high thermal performance
PCB layout, refer to the demo board application note
AN-2024.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt current paths during PC board layout. The high
current loops that do not overlap have high di/dt content that
will cause observable high frequency noise on the output pin
if the input capacitor C
LMZ12002. Therefore physically place C
sible to the LMZ12002 VIN and GND exposed pad. This will
minimize the high di/dt area and reduce radiated EMI. Addi-
tionally, grounding for both the input and output capacitor
should consist of a localized top side plane that connects to
the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
capacitor C
the FB node is high impedance, maintain the copper area as
small as possible. The trace are from R
CA
IC-LOSS
< (125 — 85) / 1.2W —1.9 = 31.4
for the application being designed. In this application
CA
FF
, should be located close to the FB pin. Since
= 31.4, the PCB is required to dissipate heat
2
= 500°C x cm
IN1
FBT
is placed a distance away for the
and R
2
/W / θ
FBB
JC
, and the feed forward
IN1
(19)
FBT
asa close as pos-
, R
FBB
www.national.com
, and C
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FF