STEVAL-IFP007V1 STMicroelectronics, STEVAL-IFP007V1 Datasheet - Page 13

• Manufacturer Part Number: STEVAL-IFP007V1
• Description: BOARD EVAL BASED ON SCLT3-8
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFP007V1

• Main Purpose: Interface, Digital Signal Termination
• Embedded: No
• Utilized Ic / Part: SCLT3-8
• Primary Attributes: 8 Channel Optical Isolation
• Secondary Attributes: SPI Interface
• Processor To Be Evaluated: SCLT3
• Data Bus Width: 16 bit
• Interface Type: SPI
• Operating Supply Voltage: 24 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-9045

SCLT3-8BT8
2.7
2.7.1
Figure 10. SPI shift register data transfer sequence versus SCLT input states
Control bit signals of the SPI transferred data frame
Power bus voltage monitoring
The UVA circuit generates the alarm /UVA that is active low when the power bus voltage is
lower than the activation threshold V
power bus voltage rises above the threshold V
The UVA circuit is robust enough to resist ESD and EFT effects, and a filter is added to
avoid drop out effects. The analog level can be adjusted externally with a pull down resistor.
The power bus voltage is sensed from a separate sensing pin V
about 15% and the alarm circuit should be insensitive to drop out of less than 1 ms.
The under voltage detection does not lead to the SCLT internal shutdown but generates an
alarm /UVA that is transmitted through the SPI on control bit #7.
/CS=”1”
/CS=”1”
SCK15
SCK15
SCK16
SCK16
SCK16
SCK16
SCK1
SCK1
SCK1
SCK1
SCK2
SCK2
SCK1
SCK1
/CS
/CS
/CS
/CS
MOSI
MOSI
MOSI
MOSI
LSB
LSB
MSB
MSB
MSB
MSB
LSB
LSB
MSB
MSB
B14
B14
B13
B13
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
B14
B14
B1
B1
0
0
0
0
0
0
0
0
LSB
LSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
B1
B1
B14
B14
B1
B1
LSB
LSB
MSB
MSB
B1
B1
B1
B1
B1
B1
B2
B2
B1
B1
B2
B2
B1
B1
B1
B1
Doc ID 15191 Rev 3
B1
B1
LSB
LSB
B2
B2
B2
B2
B2
B2
B2
B2
B3
B3
B3
B3
B2
B2
B2
B2
CON
B3
B3
B3
B3
B3
B3
B2
B2
B4
B4
B4
B4
B3
B3
B1
B1
B3
B3
B3
B3
B4
B4
B4
B4
B4
B4
B3
B3
B5
B5
B4
B4
B4
B4
B2
B2
B5
B5
B4
B4
, 17 V typical, and it is disabled high when the
B5
B5
B5
B5
B5
B5
B4
B4
B6
B6
B5
B5
B3
B3
B6
B6
B5
B5
B5
B5
B6
B6
B6
B6
B6
B6
B5
B5
B7
B7
B7
B7
B6
B6
COFF
B4
B4
B6
B6
B6
B6
B7
B7
B7
B7
B7
B7
B6
B6
B8
B8
B7
B7
B5
B5
B8
B8
B7
B7
B7
B7
, 18 V typical as shown in
B8
B8
B8
B8
B8
B8
B7
B7
B9
B9
B9
B9
B8
B8
B6
B6
B8
B8
B8
B8
B10
B10
B10
B10
B8
B8
B9
B9
B9
B9
B9
B9
B9
B9
B9
B9
B7
B7
B9
B9
B10
B10
B10
B10
B10
B10
B11
B11
B11
B11
B10
B10
B10
B10
B10
B10
B9
B9
B8
B8
B11
B11
B11
B11
B11
B11
B11
B11
B10
B10
B12
B12
B11
B11
B12
B12
B11
B11
B9
B9
CS
B12
B12
B12
B12
B12
B12
B11
B11
B13
B13
B13
B13
B12
B12
B10
B10
B12
B12
B12
B12
. The overall accuracy is
Functional description
B13
B13
B13
B13
B13
B13
B12
B12
B14
B14
B14
B14
B13
B13
B11
B11
B13
B13
B13
B13
MSB
MSB
MSB
MSB
B14
B14
B14
B14
B14
B14
B13
B13
B12
B12
B14
B14
B14
B14
B14
B14
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
B14
B14
B13
B13
Figure
MISO
MISO
MISO
MISO
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
B14
B14
LSB
LSB
B13
B13
Z
Z
Z
Z
Z
Z
12.
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