DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 7

• Manufacturer Part Number: DTMFDECODER-RD
• Description: KIT REF DESIGN DTMF DECODER
• Manufacturer: Silicon Laboratories Inc

Specifications of DTMFDECODER-RD

• Mfg Application Notes: DTMF Decoder Ref Design AppNote
• Main Purpose: Telecom, DTMF Decoder
• Embedded: No
• Utilized Ic / Part: C8051F300
• Primary Attributes: 8kHz Sampling Rate ADC
• Secondary Attributes: 16 Goertzel Filters
• Processor To Be Evaluated: C8051F300
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1283

List of Figures
1. System Overview
2. Absolute Maximum Ratings
3. Global Electrical Characteristics
4. Pinout and Package Definitions
5. ADC0 (8-Bit ADC, C8051F300/2)
6. Voltage Reference (C8051F300/2)
7. Comparator0
8. CIP-51 Microcontroller
9. Reset Sources
Figure 1.1. C8051F300/2 Block Diagram ................................................................. 15
Figure 1.2. C8051F301/3/4/5 Block Diagram ........................................................... 15
Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16
Figure 1.4. On-Chip Clock and Reset ...................................................................... 17
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 18
Figure 1.6. Development/In-System Debug Diagram............................................... 19
Figure 1.7. Digital Crossbar Diagram ....................................................................... 20
Figure 1.8. PCA Block Diagram ............................................................................... 21
Figure 1.9. PCA Block Diagram ............................................................................... 21
Figure 1.10. 8-Bit ADC Block Diagram ..................................................................... 22
Figure 1.11. Comparator Block Diagram .................................................................. 23
Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 28
Figure 4.2. QFN-11 Package Drawing ..................................................................... 29
Figure 4.3. Typical QFN-11 Solder Paste Mask....................................................... 30
Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 31
Figure 4.5. SOIC-14 Pinout Diagram (Top View) ..................................................... 32
Figure 4.6. SOIC-14 Package Drawing .................................................................... 33
Figure 4.7. SOIC-14 PCB Land Pattern ................................................................... 34
Figure 5.1. ADC0 Functional Block Diagram............................................................ 35
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 37
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 38
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 40
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 41
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 45
Figure 5.7. ADC Window Compare Examples, Differential Mode ............................ 46
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 49
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 51
Figure 7.2. Comparator Hysteresis Plot ................................................................... 52
Figure 8.1. CIP-51 Block Diagram............................................................................ 57
Figure 8.2. Program Memory Maps.......................................................................... 63
Figure 8.3. Data Memory Map.................................................................................. 64
Figure 9.1. Reset Sources........................................................................................ 83
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 84
Rev. 2.9
C8051F300/1/2/3/4/5
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