EVAL-AD7877EBZ Analog Devices Inc, EVAL-AD7877EBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD7877EBZ
• Description: BOARD EVALUATION FOR AD7877
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7877EBZ

• Main Purpose: Interface, Touch Screen Controller
• Embedded: No
• Utilized Ic / Part: AD7877
• Primary Attributes: 4-Wire Resistive Touch Screen Controller, SPI Interface, On-Chip: Temp Sensor, Voltage Reference, 8-Bit DAC
• Secondary Attributes: USB GUI, LCD Noise Reduction Feature, 2.7 ~ 5.25 V, Wake Up on Touch Feature
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7877
Figure 40. Master Mode Sequencer Operation
GO TO MODE 00
1
YES
SEE SEQUENCER REGISTERS SECTION.
YES
YES
NO
START ACQUISITION TIMER
YES
SELECTED CHANNEL
LIMIT COMPARISON
AD7877 IN MODE 11
WRITE RESULT TO
START FCD TIMER
HOST PROGRAMS
SIGNAL ACTIVE?
SIGNAL ACTIVE?
ENABLE/STATUS
TIME FINISHED?
YES
IS ACQUISITION
UPDATE ALERT
ASSERT ALERT
OUT-OF-LIMIT?
LAST CHANNEL
SCREEN STILL
SCREEN STILL
SEQUENCE 1?
IS AVERAGING
IN SEQUENCE?
SELECT NEXT
START TIMER
YES
IS STOPACQ
IS STOPACQ
REGISTERS
ONCE-ONLY
REQUIRED?
NO
FINISHED?
TOUCHED?
TOUCHED?
FINISHED?
YES
YES
ENABLED?
TOUCHED?
FINISHED?
YES
REGISTER
YES
YES
CHANNEL
CONVERT
NO
SOURCE
OUTPUT
SCREEN
ALERT
MODE?
TIMER
IS FCD
IS FCD
VALID
IS
IS
IS
YES
YES
YES
NO
NO
1
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
Rev. C | Page 24 of 44
INTERRUPTS
Data Available Output ( DAV )
The data available output ( DAV ) indicates that new ADC data
is available in the results registers. While the ADC is idle or is
converting, DAV is high. Once the ADC has finished converting
and new data has been written to the results registers, DAV goes
low. Taking DAV low to read the registers resets DAV to a high
condition. DAV is also reset, if a new conversion is started by
the AD7877 because the timer expired. The host should attempt
to read the results registers only when DAV is low.
DAV is useful as a host interrupt in master mode. In this mode,
the host can program the AD7877 to automatically perform a
sequence of conversions, and can be interrupted by DAV at the
end of each conversion sequence.
When the on-board timer is programmed to perform automatic
conversions, a limited time is available to the host to read the
results registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the results registers while DAV is high.
Figure 42 shows the worst-case timings for reading the results
registers after DAV has gone low. The timer is set at a
minimum, and the conversion sequence includes all 11 possible
ADC channels. t
conversion on one ADC channel. t
delay, that is, 1024 clock periods. t
11 result registers. If the host wants to read all 11 registers, then
it must do so before the timer expires. t
allowable between DAV going low and the host beginning to
read the results registers. If t
cannot be read before the start of a new conversion, and
incorrect data could be read by the host.
STATUS
STATUS
AD7877
AD7877
DOUT
DAV
DAV
CS
CS
IDLE
CONVERSION AND
Figure 42. Timing for Reads after DAV Goes Low
ACQUISITION
CHANNEL 11
BY HOST
1
t
SETUP
Figure 41. Operation of DAV Output
1
is the time taken for acquisition and
CONVERTING
4
t
CONV
ADC
is exceeded, then all registers
3
2
is the time taken to read all
TIMER INTERVAL
shows the minimum timer
AVAILABLE
NEW DATA
t
4
4
is the maximum time
t
2
HOST READS
RESULTS
t
3
IDLE
CHNL
1