CDB5463U Cirrus Logic Inc, CDB5463U Datasheet - Page 16

• Manufacturer Part Number: CDB5463U
• Description: BOARD EVAL & SOFTWARE CS5463 ADC
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5463U

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5463
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI Interfaces
• Product: Data Conversion Development Tools
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5463
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1553

5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5463 is equipped with two fully differential input
channels. The inputs VIN ± and IIN ± are designated as
the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
and voltage channel is ± 250 mV
5.1.1 Voltage Channel
The output of the line voltage resistive divider or trans-
former is connected to the VIN+ and VIN- input pins of
the CS5463. The voltage channel is equipped with a
10x fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is ± 250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
which is approximately 70.7% of maximum peak volt-
age. The voltage channel is also equipped with a Volt-
age
programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5463. To accommodate different current sensing el-
ements the current channel incorporates a programma-
ble gain amplifier (PGA) with two programmable input
gains. Configuration Register bit Igain (see Table 1) de-
fines the two gain selections and corresponding maxi-
mum input-signal level.
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is ± 250 mV
put signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse regis-
tration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in See Sec-
tion 5.5
The Current Gain Register also facilitates an additional
programmable gain of up to 4x. If an additional gain is
16
Gain
Table 1. Current Channel PGA Setting
Energy Pulse Output
Igain
Register ,
0
1
250mV P
-------------------- -
2
Maximum Input Range
±250 mV
±50 mV
≅
allowing
176.78mV RMS
on page 17.
P
.
for
10x
50x
an
additional
P
. The in-
applied to the voltage and/or current channel, the maxi-
mum input range should be adjusted accordingly.
5.2 IIR Filters
The current and voltage channel are equipped with a
4th-order IIR filter, that is used to compensate for the
magnitude roll off of the low-pass decimation filter. Op-
erational Mode Register bit IIR engages the IIR filters in
both the voltage and current channels.
5.3 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both chan-
nels, no error component will be generated at DC when
computing V
al Mode Register bits VHPF and IHPF activate the HPF
in the voltage and current channel respectively. When a
high-pass filter is active in only one channel, an all-pass
filter (APF) is applied to the other channel. The APF has
an amplitude response that is flat within the channel
bandwidth and is used for matching phase in systems
where only one HPF is engaged.
5.4 Performing Measurements
The CS5463 performs measurements of instantaneous
voltage (V
neous power (P
where K is the clock divider selected in the Configura-
tion Register .
The RMS voltage (V
tive power (P
samples of V
value in the Cycle Count Register and is referred to as
a “ computation cycle ”. The apparent power (S) is the
product of V
rived from the master clock (MCLK), with frequency:
Under default conditions and with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
Computation Cycle = 1 Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s comple-
ment, normalized value between -1 and +1. The format
n
) and current (I
RMS
RMS
active
n
, I
n
Computation Cycle
, I
n
) at an output word rate (OWR) of
and I
, and P
) are computed using N instantaneous
RMS
OWR
RMS
, and apparent power. Operation-
RMS
), RMS current (I
=
n
. A computation cycle is de-
(
---------------------------- -
respectively, where N is the
n
MCLK K
), and calculates instanta-
1024
=
⁄
OWR
-------------- -
)
N
RMS
CS5463
), and ac-
DS678F2