CDB5463U Cirrus Logic Inc, CDB5463U Datasheet - Page 26

• Manufacturer Part Number: CDB5463U
• Description: BOARD EVAL & SOFTWARE CS5463 ADC
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5463U

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5463
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI Interfaces
• Product: Data Conversion Development Tools
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5463
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1553

6. REGISTER DESCRIPTION
6.1 Page 0 Registers
6.1.1 Configuration Register ( Config )
26
PC[6:0]
I
EWA
Address: 0
Default = 0x000001
IMODE, IINV
iCPU
K[3:0]
gain
EWA
PC6
23
15
7
-
1.
2.
“Default” = bit status after power-on or reset
Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
PC5
22
14
ative to the current channel. Default setting is 0000000 = 0.0215 degree phase delay at 60 Hz
(when MCLK = 4.096 MHz). See Section 7.2
mation.
0 = Gain is 10 (default)
1 = Gain is 50
0 = Normal outputs (default)
10 = High-to-low pulse
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising edge logic
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K = 1 at reset.
Sets the gain of the current PGA.
Allows the E1 and E2 pins to be configured as open-collector output pins.
1 = Only the pull-down device of the E1 and E2 pins are active
Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
11 = Low-to-high pulse
Phase compensation. A 2’s complement number which sets a delay in the voltage channel rel-
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
6
-
-
PC4
21
13
5
-
-
IMODE
iCPU
PC3
20
12
4
PC2
IINV
K3
19
11
3
Phase Compensation
PC1
18
10
K2
2
-
on page 39 for more infor-
PC0
K1
17
9
1
-
CS5463
DS678F2
Igain
16
K0
8
0
-