EZ80L920210ZCO Zilog, EZ80L920210ZCO Datasheet - Page 42

• Manufacturer Part Number: EZ80L920210ZCO
• Description: KIT DEV EZ80 WEB SERVER
• Manufacturer: Zilog
• Series: eZ80®r

Specifications of EZ80L920210ZCO

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: eZ80L92
• Primary Attributes: *
• Secondary Attributes: *
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3165; EZ80L920210ZCO; Q1370684

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Operational Description
eZ80L92 Development Kit
User Manual
Note:
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
Flash Memory
The eZ80L92 Development Kit allows Flash memories between 1MB
and 4MB. The chips are housed in wide TSOP40 cases. Flash ROM
access times are 55–150ns; typically 90ns.
When accessing Flash memory, the eZ80L92 device should be configured
to operate in Intel bus mode to satisfy setup and hold times and to prevent
bus contention with a Write cycle that could possibly follow. For proper
CPU operation at 48MHz, first set the bus mode control register
CS0_BMC (I/O address
register CS0_CTL (I/O address
Bus Mode with two system clocks per bus cycle and zero wait states.
Memory Map
A memory map of the eZ80
ory and SRAM on the eZ80L92 Module are addressed when CS0 and CS1
are active Low. SRAM on the eZ80
when CS2 is active Low.
The Ethernet controller, located on the eZ80L92 Module, is mapped as an
I/O device at address
300h
F0h
PRELIMINARY
. It uses CS3.
®
) to
CPU is illustrated in Figure 10. Flash mem-
AAh
82h
®
) to
, then set the Chip Select Control
Development Platform is addressed
08h
. These settings select Intel
UM012906-0103